STK14C88-N25I datasheet, PDF - EEWORLD Datasheet

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STK14C88-N25I: Description32K X 8 NON-VOLATILE SRAM, 45 ns, CDIP32; Categorystorage; File Size233KB，13 Pages; ManufacturerETC

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STK14C88-N25I Overview

32K X 8 NON-VOLATILE SRAM, 45 ns, CDIP32

STK14C88-N25I Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	32
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	5.5 V
Minimum supply/operating voltage	4.5 V
Rated supply voltage	5 V
maximum access time	45 ns
Processing package description	0.300 INCH, SIDE BRAZED, CERAMIC, MO-058, DIP-32
state	ACTIVE
Craftsmanship	CMOS
packaging shape	RECTANGULAR
Package Size	IN-LINE
Terminal form	THROUGH-HOLE
Terminal spacing	2.54 mm
terminal coating	TIN LEAD
Terminal location	DUAL
Packaging Materials	CERAMIC, METAL-SEALED COFIRED
Temperature level	INDUSTRIAL
memory width	8
organize	32K X 8
storage density	262144 deg
operating mode	ASYNCHRONOUS
Number of digits	32768 words
Number of digits	32K
Memory IC type	NON-VOLATILE SRAM
serial parallel	PARALLEL

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STK14C88

32K x 8

AutoStore™

nvSRAM

QuantumTrap™

CMOS

Nonvolatile Static RAM

FEATURES

• 25ns, 35ns and 45ns Access Times

• “Hands-off” Automatic

STORE

with External

68µF Capacitor on Power Down

•

STORE

to nonvolatile elements Initiated by

Hardware, Software or

AutoStore™

•

RECALL

to SRAM Initiated by Software or

Power Restore

• 10mA Typical I

at 200ns Cycle Time

• Unlimited READ, WRITE and

RECALL

Cycles

• 1,000,000

STORE

Cycles to nonvolatile ele-

ments (Commercial/Industrial)

• 100-Year Data Retention in nonvolatile ele-

ments (Commercial/Industrial)

• Single 5V + 10% Operation

• Commercial, Industrial and Military Tempera-

tures

• 32-Pin SOIC, DIP and LCC Packages

DESCRIPTION

The Simtek STK14C88 is a fast static

RAM

with a

nonvolatile element incorporated in each static

memory cell. The

SRAM

can be read and written an

unlimited number of times, while independent, non-

volatile data resides in the nonvolatile elements.

Data transfers from the

SRAM

to the nonvolatile ele-

ments (the

STORE

operation) can take place auto-

matically on power down. A 68µF or larger capacitor

tied from V

CAP

to ground guarantees the

STORE

operation, regardless of power-down slew rate or

loss of power from “hot swapping”. Transfers from

the nonvolatile elements to the

SRAM

(the

RECALL

operation) take place automatically on restoration of

power. Initiation of

STORE

and

RECALL

cycles can

also be software controlled by entering specific read

sequences. A hardware

STORE

may be initiated with

the HSB pin.

BLOCK DIAGRAM

CCX

Quantum Trap

512 x 512

CAP

PIN CONFIGURATIONS

CAP

POWER

CONTROL

ROW DECODER

STORE

STATIC RAM

ARRAY

512 x 512

RECALL

STORE/

RECALL

CONTROL

HSB

CCX

HSB

32 - LCC

COLUMN I/O

COLUMN DEC

SOFTWARE

DETECT

- A

32 - DIP

32 - SOIC

INPUT BUFFERS

PIN NAMES

- A

-DQ

Address Inputs

Data In/Out

Chip Enable

Write Enable

Output Enable

Hardware Store Busy (I/O)

Power (+ 5V)

Capacitor

Ground

HSB

CCX

CAP

December 2002

Document Control # ML0014 rev 0.0

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