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19-1156; Rev 2; 6/98
+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8
__________________General Description
The MAX1242/MAX1243 are low-power, 10-bit analog-
to-digital converters (ADCs) available in 8-pin pack-
ages. They operate with a single +2.7V to +5.25V
supply and feature a 7.5µs successive-approximation
ADC, a fast track/hold (1.5µs), an on-chip clock, and a
high-speed, 3-wire serial interface.
Power consumption is only 3mW (V
DD
= 3V) at the
73ksps maximum sampling speed. A 2µA shutdown
mode reduces power at slower throughput rates.
The MAX1242 has an internal 2.5V reference, while the
MAX1243 requires an external reference. The MAX1243
accepts signals from 0V to V
REF
, and the reference
input range includes the positive supply rail. An exter-
nal clock accesses data from the 3-wire interface,
which connects directly to standard microcontroller I/O
ports. The interface is compatible with SPI™, QSPI™,
and Microwire™.
Excellent AC characteristics and very low power com-
bined with ease of use and small package size make
these converters ideal for remote-sensor and data-
acquisition applications, or for other circuits with
demanding power consumption and space require-
ments. The MAX1242/MAX1243 are available in 8-pin
DIP and SO packages.
________________________________Features
o
+2.7V to +5.25V Single-Supply Operation
o
10-Bit Resolution
o
Internal 2.5V Reference (MAX1242)
o
Small Footprint: 8-Pin DIP and SO Packages
o
Low Power: 3.7mW (73ksps, MAX1242)
3mW (73ksps, MAX1243)
66µW (1ksps, MAX1243)
5µW (power-down mode)
o
Internal Track/Hold
o
SPI™/QSPI™/Microwire™ 3-Wire Serial Interface
o
Pin-Compatible 12-Bit Upgrades:
MAX1240/MAX1241
MAX1242/MAX1243
_________________Ordering Information
PART
MAX1242ACPA
MAX1242BCPA
MAX1242ACSA
MAX1242BCSA
MAX1242AEPA
MAX1242BEPA
TEMP. RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
PIN-
PACKAGE
8 Plastic DIP
8 Plastic DIP
8 SO
8 SO
8 Plastic DIP
8 Plastic DIP
INL
(LSB)
±
1
/
2
±1
±
1
/
2
±1
±
1
/
2
±1
Applications
Portable Data Logging
Test Equipment
Isolated Data Acquisition
Process Control Monitoring
Temperature Measurement
Ordering Information continued at end of data sheet.
Note:
Order the MAX1242A in place of the MAX1242C. Order the
MAX1242B in place of the MAX1242D.
________________Functional Diagram
Pin Configuration
CS
7
8
3
CONTROL
LOGIC
INT
CLOCK
V
DD
1
SCLK
SHDN
TOP VIEW
V
DD
AIN
1
2
8
7
SCLK
CS
AIN
2
T/H
2.5V
REFERENCE
REF
4
MAX1242 ONLY
5
GND
10-BIT
SAR
OUTPUT
SHIFT
REGISTER
6
DOUT
SHDN 3
REF 4
MAX1242
MAX1243
6
5
DOUT
GND
MAX1242
MAX1243
DIP/SO
SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.
________________________________________________________________
Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8
MAX1242/MAX1243
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND .............................................................-0.3V to +6V
AIN to GND................................................-0.3V to (V
DD
+ 0.3V)
REF to GND ...............................................-0.3V to (V
DD
+ 0.3V)
Digital Inputs to GND...............................................-0.3V to +6V
DOUT to GND............................................-0.3V to (V
DD
+ 0.3V)
DOUT Current ..................................................................±25mA
Continuous Power Dissipation (T
A
= +70°C)
Plastic DIP (derate 9.09mW/°C above +70°C) ...........727mW
SO (derate 5.88mW/°C above +70°C)........................471mW
CERDIP (derate 8.00mW/°C above +70°C)................640mW
Operating Temperature Ranges
MAX1242/MAX1243_C_A ..................................0°C to +70°C
MAX1242/MAX1243_E_ A ..............................-40°C to +85°C
MAX1242/MAX1243_MJA ............................-55°C to +125°C
Storage Temperature Range............................-60°C to +150°C
Lead Temperature (soldering, 10sec)............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= +2.7V to +5.25V; 73ksps; f
SCLK
= 2.1MHz (50% duty cycle); MAX1242—4.7µF capacitor at REF pin, MAX1243—external
reference; V
REF
= 2.5V applied to REF pin; T
A
= T
MIN
to T
MAX
; unless otherwise noted.)
PARAMETER
DC ACCURACY
(Note 1)
(Note1)
Resolution
Relative Accuracy (Note 2)
Differential Nonlinearity
Offset Error
Gain Error (Note 3)
Gain Temperature Coefficient
DYNAMIC SPECIFICATIONS
(10kHz sine-wave input, 0V to 2.5Vp-p, 73ksps,
SCLK
=2.1MHz)
2.5p-p, 73ksps, f f
SCLK
= 2.1MHz)
Signal-to-Noise Plus
Distortion Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range
Small-Signal Bandwidth
Full-Power Bandwidth
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
Throughput Rate
Aperture Delay
Aperture Jitter
ANALOG INPUT
Input Voltage Range
Input Capacitance
0
16
V
REF
V
pF
t
AP
t
CONV
t
ACQ
f
SCLK
= 2.1MHz
Figure 9
30
<50
5.5
7.5
1.5
73
µs
µs
ksps
ns
ps
SINAD
THD
SFDR
-3dB rolloff
Up to the 5th harmonic
66
-70
70
2.25
1.0
dB
dB
dB
MHz
MHz
DNL
MAX124_A
MAX124_B
No missing codes over temperature
MAX124_A
MAX124_B
MAX124_A
MAX124_B
±0.25
10
±0.5
±1.0
±1
±1
±2
±1
±2
LSB
ppm/°C
LSB
Bits
LSB
LSB
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +2.7V to +5.25V; 73ksps; f
SCLK
= 2.1MHz (50% duty cycle); MAX1242—4.7µF capacitor at REF pin, MAX1243—external
reference; V
REF
= 2.5V applied to REF pin; T
A
= T
MIN
to T
MAX
; unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
T
A
= +25°C (Note 4)
MAX1242
0mA to 0.2mA output load
4.7
1.00
100
25
±0.01
V
DD
+
50mV
150
10
MIN
2.470
TYP
2.500
±30
0.35
MAX
2.530
30
UNITS
V
mA
ppm/°C
mV
µF
INTERNAL REFERENCE
(MAX1242 only)
REF Output Voltage
REF Short-Circuit Current
REF Temperature Coefficient
Load Regulation (Note 5)
Capacitive Bypass at REF
EXTERNAL REFERENCE
(VREF = 2.5V)
Input Voltage Range
Input Current
Input Resistance
REF Input Current in Shutdown
Capacitive Bypass at REF
DIGITAL INPUTS: SCLK,
CS
,
SHDN
SCLK,
CS
Input High Voltage
SCLK,
CS
Input Low Voltage
SCLK,
CS
Input Hysteresis
SCLK,
CS
Input Leakage
SCLK,
CS
Input Capacitance
SHDN
Input High Voltage
SHDN
Input Low Voltage
SHDN
Input Current
SHDN
Input Mid Voltage
SHDN
Voltage, Floating
SHDN
Max Allowed Leakage,
Mid Input
DIGITAL OUTPUT: DOUT
Output Voltage Low
Output Voltage High
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Supply Voltage
V
DD
Operating mode (MAX1242)
Operating mode (MAX1242)
Supply Current
I
DD
V
DD
= 3.6V
V
DD
= 5.25V
V
DD
= 3.6V
Operating mode (MAX1243)
V
DD
= 5.25V
V
DD
= 3.6V
Power-down
V
DD
= 5.25V
V
DD
= V
DD(min)
to V
DD(max)
, full-scale input
2.7
1.4
1.8
0.9
1.6
1.9
3.5
±0.3
5.25
2.0
3.0
1.5
2.5
10
15
V
V
OL
V
OH
I
L
C
OUT
I
SINK
= 5MA
I
SINK
= 16mA
I
SOURCE
= 0.5mA
CS
= V
DD
CS
= V
DD
(Note 6)
0.4
0.8
V
DD
- 0.5
±0.01
±10
15
V
V
µA
pF
V
SM
V
FLT
SHDN
= float
SHDN
= float
V
IH
V
IL
V
HYST
I
IN
C
IN
V
SH
V
SL
SHDN
= 0V or V
DD
1.1
V
DD
/ 2
±100
V
IN
= 0V or V
DD
(Note 6)
V
DD
- 0.4
0.4
±4.0
V
DD
- 1.1
0.2
±0.01
±1
15
V
DD
≤
3.6V
V
DD
> 3.6V
2.0
3.0
0.8
V
V
V
µA
pF
V
V
µA
V
V
nA
V
µA
kΩ
µA
µF
18
SHDN
= 0V
0.1
mA
µA
mV
3
Power-Supply Rejection (Note 7)
PSR
_______________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8
MAX1242/MAX1243
TIMING CHARACTERISTICS
(V
DD
= +2.7V to +5.25V, circuit of Figure 9, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
Acquisition Time
SCLK Fall to Output Data Valid
CS
Fall to Output Enable
CS
Rise to Output Disable
SCLK Clock Frequency
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Low to
CS
Fall Setup Time
DOUT Rise to SCLK Rise (Note 6)
CS
Pulse Width
SYMBOL
t
ACQ
t
DO
t
DV
t
TR
f
SCLK
t
CH
t
CL
t
CS0
t
STR
t
CS
Figure 1,
C
LOAD
= 50pF
Figure 1, C
LOAD
= 50pF
Figure 2, C
LOAD
= 50pF
0
200
200
50
0
240
CONDITIONS
CS
= V
DD
(Note 8)
MAX124_ _C/E
MAX124_ _M
MIN
1.5
20
20
200
240
240
240
2.1
TYP
MAX
UNITS
µs
ns
ns
ns
MHz
ns
ns
ns
ns
ns
Note 1:
Tested at V
DD
= +2.7V.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offset have been calibrated.
Note 3:
Offset nulled.
Note 4:
Sample tested to 0.1% AQL.
Note 5:
External load should not change during conversion for specified accuracy.
Note 6:
Guaranteed by design. Not subject to production testing.
Note 7:
Measured as [V
FS
(V
DD(min)
) - V
FS
(V
DD(max)
)].
Note 8:
To guarantee acquisition time, t
ACQ
is the maximum time the device takes to acquire the signal, and is also the minimum
time needed for the signal to be acquired.
+2.7V
6k
DOUT
6k
DGND
a)
High-Z to V
OH
and V
OL
to V
OH
b)
High-Z to V
OL
and V
OH
to V
OL
C
LOAD
= 50pF
DOUT
C
LOAD
= 50pF
DGND
Figure 1. Load Circuits for DOUT Enable Time
+2.7V
6k
DOUT
6k
DGND
a)
V
OH
to High-Z
b)
V
OL
to High-Z
C
LOAD
= 50pF
DOUT
C
LOAD
= 50pF
DGND
Figure 2. Load Circuits for DOUT Disable Time
4
_______________________________________________________________________________________
Wireless Connectivity
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