NS32332U-15 datasheet, PDF - EEWORLD Datasheet

NS32332U-15: Description32-BIT, 15MHz, MICROPROCESSOR, CPGA84, CERAMIC, CAVITY DOWN, PGA-84; CategoryThe embedded processor and controller Microcontrollers and processors; File Size4MB，74 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/

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NS32332U-15 Overview

32-BIT, 15MHz, MICROPROCESSOR, CPGA84, CERAMIC, CAVITY DOWN, PGA-84

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Texas Instruments
package instruction	PGA, PGA84,13X13
Reach Compliance Code	unknown
Address bus width	32
bit size	32
boundary scan	NO
maximum clock frequency	15 MHz
External data bus width	32
Format	FIXED POINT
Integrated cache	NO
JESD-30 code	S-CPGA-P84
JESD-609 code	e0
length	33.02 mm
low power mode	NO
Number of terminals	84
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Encapsulate equivalent code	PGA84,13X13
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	3.836 mm
speed	15 MHz
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	MOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED
width	33.02 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR

	NS32332U-15	NS32332U-10
Description	32-BIT, 15MHz, MICROPROCESSOR, CPGA84, CERAMIC, CAVITY DOWN, PGA-84	32-BIT, 10MHz, MICROPROCESSOR, CPGA84, CERAMIC, CAVITY DOWN, PGA-84
Is it Rohs certified?	incompatible	incompatible
Maker	Texas Instruments	Texas Instruments
package instruction	PGA, PGA84,13X13	PGA, PGA84,13X13
Reach Compliance Code	unknown	unknown
Address bus width	32	32
bit size	32	32
boundary scan	NO	NO
maximum clock frequency	15 MHz	10 MHz
External data bus width	32	32
Format	FIXED POINT	FIXED POINT
Integrated cache	NO	NO
JESD-30 code	S-CPGA-P84	S-CPGA-P84
JESD-609 code	e0	e0
length	33.02 mm	33.02 mm
low power mode	NO	NO
Number of terminals	84	84
Maximum operating temperature	70 °C	70 °C
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA	PGA
Encapsulate equivalent code	PGA84,13X13	PGA84,13X13
Package shape	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED
Certification status	Not Qualified	Not Qualified
Maximum seat height	3.836 mm	3.836 mm
speed	15 MHz	10 MHz
Maximum supply voltage	5.25 V	5.25 V
Minimum supply voltage	4.75 V	4.75 V
Nominal supply voltage	5 V	5 V
surface mount	NO	NO
technology	MOS	MOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG	PIN/PEG
Terminal pitch	2.54 mm	2.54 mm
Terminal location	PERPENDICULAR	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	33.02 mm	33.02 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR	MICROPROCESSOR

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