NATIONAL HYBRID, Inc.
Multi-Protocol Data Bus Interface
NHi-RT Expanded Memory
Remote Terminals
User's Manual
Version 2000.09.05
September 2000
The information provided in this document is believed to be accurate; however, no responsibility is assumed by NATIONAL
HYBRID, INC. for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications
are subject to change without notice.
2200 Smithtown Avenue, Ronkonkoma, NY 11779
Telephone (631) 981- 2400
Data Bus Fax (631) 981- 2445
Website http: //www.nationalhybrid.com
Email: databus@nationalhybrid.com
TABLE OF CONTENTS
1.0.0
2.0.0
3.0.0
3.1.0
3.1.1
3.1.2
3.2.0
3.3.0
3.3.1
3.3.2
3.3.3
3.3.3.1
3.3.3.1.1
3.3.3.2
3.3.4
3.3.4.1
3.3.4.2
3.3.4.3
3.3.4.4
3.3.4.5
3.3.4.6
3.3.5
3.4.0
4.0.0
4.1.0
4.2.0
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
4.2.10
4.2.11
4.2.12
4.2.13
4.2.14
4.2.15
4.2.16
4.2.17
4.2.18
4.2.19
4.2.20
4.2.21
4.2.22
4.2.23
SCOPE.
.
.
.
.
Nhi-RT PROTOCOL COMPLIANCE
.
INTRODUCTION
.
.
.
FEATURES
.
.
.
.
GENERAL FEATURES
.
.
REMOTE TERMINAL HIGHLIGHTS
.
BLOCK DIAGRAM
.
.
.
PROTOCOL CHIP DESCRIPTION
.
HOST BUS INTERFACE UNIT
.
.
I/O BUS INTERFACE UNIT
.
.
INTERRUPT CONTROL UNIT .
.
ICU REGISTERS
.
.
.
INTERRUPT DEFINITION TABLE
.
ICU FIFO
.
.
.
.
DUAL REDUNDANT FRONT END
.
MANCHESTER DECODER
.
.
MANCHESTER ENCODER
.
.
GAP COUNTER
.
.
.
RT - RT NO RESPONSE COUNTER .
MINIMUM RESPONSE TIME COUNTER
FAIL -SAFE TIMEOUT COUNTER
.
MESSAGE PROCESSOR UNIT
.
RT HARDWIRE TERMINAL ADDRESS.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
4
4
4
4
4
5
6
6
7
7
7
7
7
8
8
8
9
9
9
9
9
9
9
10
10
12
12
13
14
15
15
15
15
16
16
18
18
18
18
18
18
19
19
19
19
20
20
20
21
DATA STRUCTURE
.
.
.
.
ADDRESS MAP
.
.
.
.
INTERNAL REGISTERS
.
.
.
CONTROL
.
.
.
.
.
POINTER TABLE ADDRESS
.
.
.
BASIC STATUS
.
.
.
.
INTERRUPT REQUEST
.
.
.
INTERRUPT MASK
.
.
.
.
INTERRUPT VECTOR .
.
.
.
AUXILIARY VECTOR REGISTER
.
.
REAL- TIME CLOCK
.
.
.
.
RTC CONTROL REGISTER .
.
.
FIFO READ
.
.
.
.
.
FIFO RESET .
.
.
.
.
LAST COMMAND REGISTER .
.
.
LAST STATUS REGISTER
.
.
.
RESET REMOTE TERMINAL
.
.
ENCODER STATUS .
.
.
.
CONDITION REGISTER
.
.
.
ENCODER DATA REGISTER
.
.
ENCODER DATA TRANSMIT RQST .
.
ENCODER COMMAND TRANSMIT REQUEST
EXTERNAL TERMINAL ADDRESS REGISTER
COMMAND OUTPUT PINS
.
.
.
I/ O TAG WORD REGISTER .
.
.
CONFIGURATION REGISTER
1
.
.
-
1
-
TABLE OF CONTENTS(continued)
4.3.0
4.3.1
4.3.2
4.3.3
4.3.4
4.3.4.1
4.3.4.2
4.3.4.3
5.0.0
5.1.0
5.2.0
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
5.2.9
5.2.10
5.2.11
5.2.12
5.2.13
5.2.14
5.2.15
5.2.16
5.2.17
5.2.18
6.0.0
6.1.0
6.2.0
7.0.0
7.1.0
7.2.0
8.0.0
9.0.0
9.1.0
9.2.0
9.3.0
9.4.0
10.0.0
10.1.0
10.2.0
10.3.0
10.4.0
11.0.0
11.0.1
RT DATA TABLES
.
.
.
.
.
MESSAGE ILLEGALITY
.
.
.
.
DATA TABLE TAG WORD
.
.
.
.
DATA TABLE POINTER
.
.
.
.
RT DATA TABLE BUFFERING SCHEME
.
.
RT RAM ACCESS
.
.
.
.
.
HOST RAM ACCESS
.
.
.
.
.
READ- MODIFY- WRITE
.
.
.
.
RT MODE CODE OPERATION
.
.
.
.
GENERAL
.
.
.
.
.
.
TABLE OF RT MODE CODE RESPONSES
.
.
DYNAMIC BUS CONTROL (00000; T/R=1)
.
.
SYNCHRONIZE WITHOUT DATA
(00001; T/R=1)
.
TRANSMIT LAST STATUS WORD (00010; T/R=1)
.
INITIATE SELF TEST (00011; T/R=1) .
.
.
TRANSMITTER SHUTDOWN
(00100; T/R=1) .
.
OVERRIDE TRANSMITTER SHUTDOWN
.
.
(00101; T/R=1)
INHIBIT TERMINAL FLAG (00110; T/R=1)
.
.
OVERRIDE INHIBIT TERMINAL FLAG
(00110; T/R=1) .
RESET REMOTE TERMINAL (01000; T/ R= 1) .
.
RESERVED MODE CODES (01001- 01111; T/ R= 1) .
TRANSMIT VECTOR WORD
(10000; T/ R= 1) .
.
SYNCHRONIZE WITH DATA WORD (10001; T/ R= 0) .
TRANSMIT LAST COMMAND
(10010; T/ R= 1).
.
TRANSMIT BIT WORD (10011; T/ R= 1)
.
.
SELECTED TRANSMITTER SHUTDOWN
.
.
(10100; T/ R= 0)
OVERRIDE SELECTED TRANSMITTER SHUTDOWN
.
(10101; T/ R= 0)
RESERVED MODE CODES (10110- 11111; T/ R= 1) .
RESERVED MODE CODES
(10110- 11111; T/ R= 0) .
INITIALIZATION
.
.
.
.
.
INTERNAL INITIALIZATION .
.
.
.
HOST INITIALIZATION OF NHi-RT
.
.
.
INTERRUPT HANDLING
.
.
.
.
HARDWARE INTERRUPT ACKNOWLEDGE .
.
SOFTWARE INTERRUPT ACKNOWLEDGE
.
.
PC BOARD CONSIDERATIONS AND GUIDE LINES .
PIN FUNCTIONAL DESCRIPTION
.
.
.
GENERAL PURPOSE SIGNALS
.
.
.
HOST INTERFACE SIGNALS .
.
.
.
DISCRETE I/O BUS INTERFACE SIGNALS
.
.
MIL BUS INTERFACE SIGNALS
.
.
.
ELECTRICAL CHARACTERISTICS
.
.
.
ABSOLUTE MAXIMUM RATINGS
.
.
.
OPERATING CONDITIONS
.
.
.
.
I/O TYPES & DESCRIPTIONS
.
.
.
.
I/O ELECTRICAL CHARACTERISTICS
.
.
TIMING DIAGRAMS
.
.
.
.
.
HOST WRITE CYCLE .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
21
22
23
24
24
24
25
25
26
26
26
26
27
27
27
28
28
28
29
29
29
30
30
31
31
31
32
32
33
33
33
34
35
35
36
36
37
37
37
38
39
39
39
39
40
40
41
41
-
2
-
TABLE OF CONTENTS(continued)
11.0.2
11.0.3
11.0.4
11.0.5
11.0.6
11.0.7
11.0.8
11.0.9
11.0.10
11.1.0
11.1.1
11.1.2
11.1.3
11.1.4
12.0.0
12.0.1
12.1.0
12.1.1
12.1.2
12.1.3
12.1.4
12.1.5
13.0.0
14.0.0
HOST READ CYCLE .
.
.
.
.
HOST READ- MODIFY- WRITE CYCLE
.
.
RT HARDWARE INTERRUPT ACKNOWLEDGE CYCLE
I/O WRITE CYCLE
.
.
.
.
.
I/O READ CYCLE
.
.
.
.
.
COMMAND WRITE CYCLE
.
.
.
.
TERMINAL ADDRESS READ CYCLE .
.
.
SOFTWARE INTERRUPT ACKNOWLEDGE CYCLE
.
TIMING DIAGRAM NOTES
.
.
.
.
TIMING PARAMETER TABLES
.
.
.
HOST READ, WRITE; READ- MODIFY- WRITE TABLE
SOFTWARE INTERRUPT ACKNOWLEDGE
I/O READ and TERMINAL ADDRESS READ TABLE .
I/O WRITE and COMMAND WRITE TABLE
.
.
RT HARDWARE INTERRUPT ACKNOWLEDGE TABLE
PIN FUNCTIONS
.
.
.
.
.
NHi-15191RT,192RT,984RT,985RT- QUAD FLAT PACK and
PGA .
.
GENERIC PACKAGE OUTLINE DRAWINGS
.
.
QUAD FLAT PACK UNFORMED LEADS
.
.
QUAD FLAT PACK GULL WING LEADS
.
.
PIN GRID ARRAY
.
.
.
.
.
MICRO QUAD FLAT PACK UNFORMED LEADS
.
MICRO QUAD FLAT PACK GULL WING LEADS
.
MATING TRANSFORMER REFERENCE
.
.
ORDERING INFORMATION
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
41
42
42
43
43
44
44
45
45
46
46
46
46
47
48
48
49
49
49
50
51
51
52
53
-
3
-
1.0.0
SCOPE
This document defines the functional and electrical specification for National Hybrid's
series of MIL- STD- Data Bus Expanded Memory Remote Terminals (NHi- RT).
2.0.0
NHi-RT PROTOCOL COMPLIANCE
MIL- STD- 1553A
MIL- STD- 1553B Notices I and II
MIL- STD- 1760B
MCAIR MDC A3818, A5690, A4905, A5332
EFA/ STANAG- 3838 requirements for Eurofighter Aircraft
3.0.0
INTRODUCTION
The NHi- RT is a low cost complete
Multi-Protocol
Mil- Std- Data Bus Interface between a dual
redundant bus and a host processor. The device functions as a programmable Remote Terminal
containing a protocol chip, two +5V monolithic transceivers and 16K word SRAM. The unit is
available packaged in a 1.1" x 1.1" 69 pin ceramic PGA, or 1.1" x 1.1" 68 pin ceramic quad
flatpack. The only external components required are two coupling transformers.
The NHi- RT appears to the host computer as 16K words of 16 bit wide memory controlled by
standard RAM signals. The device can thus be easily interfaced with all popular processors and
buses. The built in interrupt controller supports an internal FIFO which retains header information
for queuing up to 6 pending interrupt requests plus an overflow interrupt.
All modes of operation access data tables via pointers residing in RAM which facilitates multiple
buffering. This allows buffers to change without moving data and promotes efficient use of RAM
space. The data tables have programmable sizes and locations.
The NHi-RT is plug in compatible with the popular NHi-ET full function family and the 4K word
remote terminal family with no changes to hardware or software required.
3.1.0
FEATURES
The NHi- RT 16K word family is form, fit, and function compatible to all the NHi- data bus
interface parts. This interchange ability gives the user a high degree of flexibility when configuring
a system around the NHi family of parts.
3.1.1
GENERAL FEATURES
•
Mulit-Protocol Interface
•
Single +5 volt supply.
•
Operates from 10 Mhz clock.
•
Contains two monolithic +5V transceivers
•
Appears to host as a Dual Port Double Buffered 16K x 16 SRAM
•
Footprint less than 1.00 square inches
•
Ensures integrity of all shared data and control structures
•
Built- in interrupt controller
•
Internal FIFO is configurable to retain header information for queuing up to 6 pending interrupt
requests plus an overflow interrupt, or as a 7 interrupt revolving FIFO
•
Provides interrupt priority input and output pins for daisy- chaining interrupt requests
•
Contains a Timer Unit which provides 32 bit RTC (Real- Time- Clock) with 1, 2, 4, 8, 16, 32 and
64 uS internal, or user provided external clock resolution for data and event time tagging.
•
Interfaces with an 8 bit discrete I/ O bus
•
Selectable 768/ 672 us Failsafe Timer with complete Testability
•
Low power CMOS technology
-
4
-
京公网安备 11010802033920号
EEWORLD
