MM74HC165 Parallel-in/Serial-out 8-Bit Shift Register
September 1983
Revised February 1999
MM74HC165
Parallel-in/Serial-out 8-Bit Shift Register
General Description
The MM74HC165 high speed PARALLEL-IN/SERIAL-OUT
SHIFT REGISTER utilizes advanced silicon-gate CMOS
technology. It has the low power consumption and high
noise immunity of standard CMOS integrated circuits,
along with the ability to drive 10 LS-TTL loads.
This 8-bit serial shift register shifts data from Q
A
to Q
H
when clocked. Parallel inputs to each stage are enabled by
a low level at the SHIFT/LOAD input. Also included is a
gated CLOCK input and a complementary output from the
eighth bit.
Clocking is accomplished through a 2-input NOR gate per-
mitting one input to be used as a CLOCK INHIBIT function.
Holding either of the CLOCK inputs high inhibits clocking,
and holding either CLOCK input low with the SHIFT/LOAD
input high enables the other CLOCK input. Data transfer
occurs on the positive going edge of the clock. Parallel
loading is inhibited as long as the SHIFT/LOAD input is
HIGH. When taken LOW, data at the parallel inputs is
loaded directly into the register independent of the state of
the clock.
The 74HC logic family is functionally as well as pin-out
compatible with the standard 74LS logic family. All inputs
are protected from damage due to static discharge by inter-
nal diode clamps to V
CC
and ground.
Features
s
Typical propagation delay: 20 ns (clock to Q)
s
Wide operating supply voltage range: 2–6V
s
Low input current: 1
µA
maximum
s
Low quiescent supply current: 80
µA
maximum (74HC
Series)
s
Fanout of 10 LS-TTL loads
Ordering Code:
Order Number
MM74HC165M
MM74HC165SJ
MM74HC165MTC
MM74HC165
Package Number
M16A
M16D
MTC16
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Function Table
Inputs
Internal Output
Q
H
h
Q
H0
Q
GN
Q
GN
Q
H0
A. . .H Q
A
X
L
↑
↑
X
X
X
H
L
X
a. . .h
X
X
X
X
a
H
L
Q
B
b
Q
AN
Q
AN
Shift/ Clock Clock Serial Parallel Outputs
Load Inhibit
L
H
H
H
H
X
L
L
L
H
Q
A0
Q
B0
Q
A0
Q
B0
H
=
HIGH Level (steady state), L
=
LOW Level (steady state)
X
=
Irrelevant (any input, including transitions)
↑ =
Transition from LOW-to-HIGH level
Q
A0
, Q
B0
, Q
H0
=
The level of Q
A
, Q
B
, or Q
H
, respectively, before the indi-
cated steady-state input conditions were established.
Q
AN
, Q
GN
=
The level of Q
A
or Q
G
before the most recent
↑
transition of the
clock; indicates a one-bit shift.
Top View
© 1999 Fairchild Semiconductor Corporation
DS005316.prf
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MM74HC165
Absolute Maximum Ratings
(Note 1)
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Clamp Diode Current (I
IK
, I
OK
)
DC Output Current, per pin (I
OUT
)
DC V
CC
or GND Current, per pin (I
CC
)
Storage Temperature Range (T
STG
)
Power Dissipation (P
D
)
(Note 3)
S.O. Package only
Lead Temperature (T
L
)
(Soldering 10 seconds)
260°C
600 mW
500 mW
−0.5
to
+7.0V
−1.5
to V
CC
+1.5V
−0.5
to V
CC
+0.5V
±20
mA
±25
mA
±50
mA
−65°C
to
+150°C
Recommended Operating
Conditions
Min
Supply Voltage (V
CC
)
DC Input or Output Voltage
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
)
Input Rise or Fall Times
(t
r
, t
f
) V
CC
=
2.0V
V
CC
=
4.5V
V
CC
=
6.0V
1000
500
400
ns
ns
ns
0
−40
V
CC
+85
V
°C
2
Max
6
Units
V
Note 1:
Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2:
Unless otherwise specified all voltages are referenced to ground.
Note 3:
Power Dissipation temperature derating — plastic “N” package:
−
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
(Note 4)
V
CC
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
T
A
=
25°C
Typ
1.5
3.15
4.2
0.5
1.35
1.8
2.0
4.5
6.0
4.2
5.7
0
0
0
0.2
0.2
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
8.0
T
A
= −40
to 85°C T
A
= −55
to 125°C
Guaranteed Limits
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1.0
80
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1.0
160
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
Conditions
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
20
µA
2.0V
4.5V
6.0V
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
4.0 mA
|I
OUT
|
≤
5.2 mA
4.5V
6.0V
2.0V
4.5V
6.0V
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
4.0 mA
|I
OUT
|
≤
5.2 mA
4.5V
6.0V
6.0V
6.0V
V
OL
Maximum LOW Level
Output Voltage
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
20
µA
I
IN
I
CC
Maximum Input
Current
Maximum Quiescent
Supply Current
V
IN
=
V
CC
or GND
V
CC
=
2−6V
V
IN
=
V
CC
or GND
I
OUT
=
0
µA
V
CC
=
2−6V
Note 4:
For a power supply of 5V
±10%
the worst case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
=
5.5V and 4.5V respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage cur-
rent (I
IN
, I
CC
, and I
OZ
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3
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MM74HC165
AC Electrical Characteristics
V
CC
=
5V, T
A
=
25
°
C, C
L
=
15 pF, t
r
=
t
f
=
6 ns
Symbol
f
MAX
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PHL
, t
PLH
t
S
t
S
t
S
t
H
Parameter
Maximum Operating Frequency
Maximum Propagation Delay H to Q
H
or Q
H
Maximum Propagation Delay
Serial Shift/Parallel Load to Q
H
Maximum Propagation Delay
Clock to Output
Minimum Setup Time Serial Input
to Clock, Parallel or Data to Shift/Load
Minimum Setup Time Shift/Load to Clock
Minimum Setup Time Clock Inhibit to Clock
Minimum Hold Time Serial
Input to Clock or
Parallel Data to Shift/Load
t
W
Minimum Pulse Width Clock
16
ns
11
10
20
20
0
ns
ns
ns
10
20
ns
15
25
ns
Conditions
Typ
50
15
13
Guaranteed
Limit
30
25
25
Units
MHz
ns
ns
AC Electrical Characteristics
C
L
=
50 pF, t
r
=
t
f
=
6 ns (unless otherwise specified)
Symbol
f
MAX
Parameter
Maximum Operating
Frequency
t
PHL
, t
PLH
Maximum Propagation
Delay H to Q
H
or Q
H
t
PHL
, t
PLH
Maximum Propagation
Delay Serial Shift/
Parallel Load to Q
H
t
PHL
, t
PLH
Maximum Propagation
Delay Clock to Output
t
S
Minimum Setup Time
Serial Input to Clock,
or Parallel Data to Shift/Load
t
S
Minimum Setup Time
Shift/Load to Clock
t
S
Minimum Setup Time
Clock Inhibit to Clock
t
H
Minimum Hold Time Serial
Input to Clock or
Parallel Data to Shift/Load
t
W
Minimum Pulse Width,
Clock
t
THL
, t
TLH
Maximum Output
Rise and Fall Time
t
r
, t
f
Maximum Input Rise and
Fall Time
Conditions
V
CC
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
30
9
8
30
9
8
T
A
=
25°C
Typ
10
45
50
70
21
18
70
21
18
70
21
18
35
11
9
38
12
9
35
11
9
5
27
32
150
30
26
175
35
30
150
30
26
100
20
17
100
20
17
100
20
17
0
0
0
80
16
14
75
15
13
1000
500
400
T
A
= −40
to 85°C T
A
= −55
to 125°C
Guaranteed Limits
4
21
25
189
38
33
220
44
37
189
38
33
125
25
21
125
25
21
125
25
21
0
0
0
100
20
18
95
19
16
1000
500
400
4
18
21
225
45
39
260
52
44
225
45
39
150
30
25
150
30
25
150
30
25
0
0
0
120
24
20
110
22
19
1000
500
400
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
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