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AS7C252MPFS18A-200BC

Description
Standard SRAM, 2MX18, 6.5ns, CMOS, PBGA165, BGA-165
Categorystorage    storage   
File Size563KB,22 Pages
ManufacturerALSC [Alliance Semiconductor Corporation]
Download Datasheet Parametric View All

AS7C252MPFS18A-200BC Overview

Standard SRAM, 2MX18, 6.5ns, CMOS, PBGA165, BGA-165

AS7C252MPFS18A-200BC Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerALSC [Alliance Semiconductor Corporation]
Parts packaging codeBGA
package instructionLBGA, BGA165,11X15,40
Contacts165
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time6.5 ns
Other featuresFLOW-THROUGH OR PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)200 MHz
I/O typeCOMMON
JESD-30 codeR-PBGA-B165
JESD-609 codee0
length17 mm
memory density37748736 bit
Memory IC TypeSTANDARD SRAM
memory width18
Number of functions1
Number of terminals165
word count2097152 words
character code2000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize2MX18
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLBGA
Encapsulate equivalent codeBGA165,11X15,40
Package shapeRECTANGULAR
Package formGRID ARRAY, LOW PROFILE
Parallel/SerialPARALLEL
power supply2.5 V
Certification statusNot Qualified
Maximum seat height1.46 mm
Maximum standby current0.06 A
Minimum standby current2.38 V
Maximum slew rate0.4 mA
Maximum supply voltage (Vsup)2.625 V
Minimum supply voltage (Vsup)2.375 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
width15 mm
April 2004
®
AS7C252MPFS18A
2.5V 2M
×
18 pipelined burst synchronous SRAM
Features
Organization: 2,097,152 words × 18 bits
Fast clock speeds to 200 MHz in LVTTL/LVCMOS
Fast clock to data access: 3.1/3.4/3.8 ns
Fast OE access time: 3.1/3.4/3.8 ns
Fully synchronous register-to-register operation
Single register flow-through mode
Single-cycle deselect
- Dual-cycle deselect also available (AS7C252MPFD18A,
AS7C251MPFD32A/AS7C251MPFD36A)
Asynchronous output enable control
Available in 100-pin TQFP and 165-ball BGA packages
Individual byte write and global write
Multiple chip enables for easy expansion
2.5V core power supply
Linear or interleaved burst control
Snooze mode for reduced power-standby
Common data inputs and data outputs
Boundary scan using IEEE 1149.1 JTAG function
NTD™
1
pipelined architecture available
(AS7C252MNTD18A, AS7C251MNTD32A/
AS7C251MNTD36A)
1 NTD™ is a trademark of Alliance Semiconductor Corporation. All
trademarks mentioned in this document are the property of their
respective owners.
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[20:0]
CLK
CS
CLR
Burst logic
Q
21
CS
Address
D
21
19 21
2M x 18
Memory
array
18
18
register
CLK
GWE
BW
b
BWE
BW
a
CE0
CE1
CE2
D
DQb
Q
CLK
D
DQa
Q
Byte Write
registers
Byte Write
CLK
D
registers
2
OE
Enable
Q
register
CE
CLK
ZZ
Output
registers
CLK
Input
registers
CLK
Power
down
D
Enable
Q
delay
register
CLK
OE
18
FT
DQ[a,b]
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
-200
5
200
3.1
400
120
70
-167
6
167
3.4
350
110
70
-133
7.5
133
3.8
325
100
70
Units
ns
MHz
ns
mA
mA
mA
4/26/04, v.1.0
Alliance Semiconductor
1 of 22
Copyright © Alliance Semiconductor. All rights reserved.
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