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LP3928 High Speed Bi-Directional Level Shifter and Ultra Low-Dropout CMOS Voltage Regulator
October 2002
LP3928
High Speed Bi-Directional Level Shifter and Ultra
Low-Dropout CMOS Voltage Regulator
General Description
The LP3928 is designed for portable and wireless applica-
tions with demanding performance and space requirements.
The LP3928 provides level shifting and power conversion
needed for applications interfacing differing voltage levels.
The part contains a bi-directional level shifter for three sig-
nals to translate the levels between 1.8V and 2.85V and an
ultra low-dropout CMOS 2.85V voltage regulator.
The three level shifted signals are individually direction con-
trolled. Signals going from 2.85V to 1.8V can also be latched
using an external clock source. The latches are powered
from internal 2.85V. There is also an option to by-pass the
latches.
The built-in low-dropout voltage regulator is ideal for mobile
phone and battery powered wireless applications. It provides
up to 150 mA from a 3.05V to 6.0V input, and is character-
ized by extremely low dropout voltage, low quiescent current
and low output noise voltage. It is stable with small 1.5 µF
±
30% ceramic and high quality tantalum output capacitors,
requiring smallest possible PC board area.
A shutdown mode is available for the level shifters and the
regulator. High performance is achieved over various load
conditions with very low rise and fall times.
n
2 ns rise and fall times (typ.)
n
20 ns direction switch response time
n
2 µA input/output leakage current
Low-Dropout Regulator:
n
3.05V to 6.0V input range
n
150 mA guaranteed output
n
Fast Turn-On time: 200 µs (typ.)
n
100 mV maximum dropout with 150 mA load
Features
n
Ultra small micro SMD package
n
Bi-directional level-shifter for three individual signals:
1.8V to 2.85V and 2.85V to 1.8V signal level translation
n
Logic controlled enable pins: 4 different operation
modes
n
LDO stable with ceramic and high quality tantalum
capacitors
n
Thermal shutdown
Applications
n
n
n
n
Multi-Media Cards for Cellular Phones
SD Cards for Cellular Handsets
Logic Level Translation
Portable Information Appliances
Key Specifications
Level Shifter:
n
4 ns propagation delay (typ.)
© 2002 National Semiconductor Corporation
DS200391
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LP3928
Typical Application Circuit
20039101
Block Diagram
20039102
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2
LP3928
Package Outline and Connection Diagrams
20039104
Note:
The actual physical placement of the package marking will vary from
part to part. The package marking “XY” will designate the date code, “TT” is
a NSC internal code for die traceability. Both will vary considerably. L8B
identifies the device.
Top View
20039103
Bottom View
16 Bump micro SMD Package
See NSC Package Number TLA16AAA
Pin Description
Pin Name
A1
A2
A3
B1
B2
B3
DIR1
DIR2
DIR3
V
CCA
V
CCB
V
BAT
GND
EN1
EN2
LatchClk
micro SMD
Bump Identifier
C4
D4
D3
C1
D1
D2
B3
B2
C3
B4
B1
A1
A3
A4
A2
C2
1.8V
1.8V
2.85V
Logic Level
1.8V
1.8V
1.8V
2.85V
2.85V
2.85V
1.8V
1.8V
1.8V
1.8V I/O Channel, (Note 1)
1.8V I/O Channel, (Note 1)
1.8V I/O Channel, (Note 1)
2.85V I/O Channel, (Note 1)
2.85V I/O Channel, (Note 1)
2.85V I/O Channel, (Note 1)
Direction control input Channel 1: ‘1’: A
→
B; 0; B
→
A
Direction control input Channel 2: ‘1’: A
→
B; 0; B
→
A
Direction control input Channel 3: ‘1’: A
→
B; 0; B
→
A
IC supply to the 1.8V side
IC supply, 2.85V output from LDO
LDO supply, Battery voltage
Power ground connection
Mode pin 1, see
Table 1
for modes and settings
Mode pin 2, see
Table 1
for modes and settings
Clock input: rising edge latches B inputs (DIR=0, normal mode)
Function
Note 1:
Pin pairs A1–B1, A2–B2 and A3–B3 form 3 independent bi-directional level-shifting channels.
TABLE 1. Operation Modes
Inputs
EN1
0
0
1
1
EN2
0
1
0
1
Level shifter off: High Z state on A
1
–A
3
, B
1
–B
3
, LDO off
Level shifter off: High Z state on A
1
–A
3
, B
1
–B
3
, LDO on
Latch bypassed in B to A direction, LDO=on (Note 2)
ON, normal mode (latch active)
State
Note 2:
LatchClk is not used here. It should not be left floating.
3
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LP3928
Pin Description
(Continued)
TABLE 2. Direction Control and LatchCLK (Normal Mode)
Inputs
Outputs and Direction
LatchClk
X
↓
↑
DIRx
1
0
0
Ax to Bx
No change (on Ax)
Bx to Ax, see example
Example for Latch Mode, DIR1 = ‘0’, EN1 = EN2 = ‘1’ (delay not shown):
20039105
Ordering Information
For micro SMD Package
Output Voltage (V)
2.85
Grade
STD
LP3928 Supplied As 250 Units, Tape & Reel
LP3928TL-1828
LP3928 Supplied As 3000 Units, Tape & Reel
LP3928TLX-1828
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