sion is provided by an active LOW Chip Enable (CE), an active
LOW Output Enable (OE), and three-state drivers. Writing to
the device is accomplished by taking Chip Enable (CE) and
Write Enable (WE) inputs LOW. Data on the four I/O pins (I/O
0
through I/O
3
) is then written into the location specified on the
address pins (A
0
through A
19
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The four input/output pins (I/O
0
through I/O
3
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1046V33 is available in a standard 400-mil-wide
32-pin SOJ package with center power and ground (revolution-
ary) pinout.
Functional Description
The CY7C1046V33 is a high-performance CMOS static RAM
organized as 1,048,576 words by 4 bits. Easy memory expan-
Logic Block Diagram
Pin Configuration
SOJ
Top View
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
INPUT BUFFER
I/O
0
SENSE AMPS
1M x 4
ARRAY
I/O
1
I/O
2
I/O
3
CE
WE
COLUMN
DECODER
POWER
DOWN
A
0
A
1
A
2
A
3
A
4
CE
I/O
0
V
CC
GND
I/O
1
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
19
A
18
A
17
A
16
A
15
OE
I/O
3
GND
V
CC
I/O
2
A
14
A
13
A
12
A
11
A
10
NC
ROW DECODER
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
OE
1046V33–1
1046V33–2
Selection Guide
7C1046V33-10
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby
Current (mA)
Shaded areas contain pre-release information.
7C1046V33-12
12
140
8
0.5
7C1046V33-15
15
130
8
0.5
10
150
Com’l
L version
8
0.5
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
June 4, 1999
ADVANCE INFORMATION
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[1]
.... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
.................................–0.5V to V
CC
+ 0.5V
CY7C1046V33
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Commercial
Ambient
Temperature
[2]
0°C to +70°C
V
CC
3.0V - 3.6V
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Load Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
GND < V
I
< V
CC
GND < V
OUT
< V
CC
,
Output Disabled
V
CC
= Max.
,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f=0
Com’l
L version
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
7C1046V33-10 7C1046V33-12 7C1046V33-15
Min.
2.4
0.4
2.2
–0.5
–1
–1
V
CC
+ 0.5
0.8
+1
+1
150
20
2.2
–0.5
–1
–1
Max.
Min.
2.4
0.4
V
CC
+ 0.5
0.8
+1
+1
140
20
2.2
–0.5
–1
–1
Max.
Min.
2.4
0.4
V
CC
+ 0.5
0.8
+1
+1
130
20
Max.
Unit
V
V
V
V
µA
µA
mA
mA
I
SB2
8
0.5
8
0.5
8
0.5
mA
Shaded areas contain pre-release information.
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input Capacitance
I/O Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 3.3V
Max.
6
6
Unit
pF
pF
Note:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. T
A
is the “Instant On” case temperature.
3. Tested initially and after any design or process changes that may affect these parameters.
2
ADVANCE INFORMATION
AC Test Loads and Waveforms
R1 317Ω
3.3V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R2
351Ω
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R2
351Ω
GND
≤
3 ns
R1 317
Ω
CY7C1046V33
ALL INPUT PULSES
3.3V
90%
10%
90%
10%
≤
3 ns
3.3V
OUTPUT
(a)
1046V33–3
1046V33–4
Equivalent to:
THÉVENIN EQUIVALENT
167Ω
1.73V
OUTPUT
Switching Characteristics
[4]
Over the Operating Range
7C1046V33-10
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[6]
OE HIGH to High Z
[5, 6]
CE LOW to Low Z
[6]
CE HIGH to High Z
[5, 6]
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[6]
WE LOW to High Z
[5, 6]
10
7
7
0
0
7
5
0
3
5
0
10
12
8
8
0
0
8
6
0
3
6
3
5
0
12
15
10
10
0
0
10
8
0
3
7
0
5
3
6
0
15
3
10
4
0
6
3
7
10
10
3
12
6
0
7
12
12
3
15
7
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C1046V33-12
Min.
Max.
7C1046V33-15
Min.
Max.
Unit
WRITE CYCLE
[7, 8]
Shaded areas contain pre-release information.
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
5. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
3
ADVANCE INFORMATION
s
CY7C1046V33
Data Retention Characteristics
Over the Operating Range
Parameter
V
DR
I
CCDR
t
CDR[3]
t
R[9]
Description
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
Com’l
V
CC
= V
DR
= 2.0V,
CE > V
CC
– 0.3V
V
IN
> V
CC
– 0.3V or V
IN
< 0.3V
Conditions
[10]
Min.
2.0
200
0
10
Max
Unit
V
µA
ns
µs
Notes:
9. t
r
< 3 ns for the -10, -12, and -15 speeds.
10. No input may exceed V
CC
+ 0.5V.
Data Retention Waveform
DATA RETENTION MODE
V
CC
3.0V
t
CDR
CE
1046V33–5
V
DR
> 2V
3.0V
t
R
Switching Waveforms
Read Cycle No. 1
[11, 12]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
1046V33–6
Read Cycle No. 2 (OE Controlled)
[12, 13]
ADDRESS
t
RC
CE
t
ACE
OE
t
DOE
DATA OUT
V
CC
SUPPLY
CURRENT
t
LZOE
HIGH IMPEDANCE
t
LZCE
t
PU
50%
t
HZOE
t
HZCE
DATA VALID
t
PD
50%
1046V33-7
HIGH
IMPEDANCE
I
CC
I
SB
Notes:
11. Device is continuously selected. OE, CE = V
IL
.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
4
ADVANCE INFORMATION
Switching Waveforms
(continued)
Write Cycle No. 1 (CE Controlled)
[14, 15]
t
WC
ADDRESS
t
SCE
CE
t
SA
t
SCE
t
AW
t
PWE
WE
t
SD
DATA I/O
DATA VALID
t
HD
t
HA
CY7C1046V33
1046V33–8
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
[14, 15]
t
WC
ADDRESS
t
SCE
CE
t
AW
t
SA
WE
t
PWE
t
HA
OE
t
SD
DATA I/O
NOTE 16
t
HZOE
1046V33–9
t
HD
DATA
IN
VALID
Notes:
14. Data I/O is high impedance if OE = V
IH
.
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
16. During this period the I/Os are in the output state and input signals should not be applied.
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