QL3004 pASIC 3 FPGA Data Sheet
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4,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance
and High Density
Device Highlights
High Performance & High Density
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4,000 Usable PLD Gates with 74 I/Os
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300 MHz 16-bit Counters,
Eight Low-Skew Distributed
Networks
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Two array clock/control networks available
400 MHz Datapaths
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0.35
µm
four-layer metal non-volatile
CMOS process for smallest die sizes
Easy to Use / Fast Development
Cycles
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100% routable with 100% utilization and
to the logic cell flip-flop clock, set and reset
inputs — each driven by an input-only pin
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Six global clock/control networks available
to the logic cell; F1, clock set, reset inputs
and the input, I/O register clock, reset, and
enable inputs as well as the output enable
control — each driven by an input-only or
I/O pin, or any logic cell output or I/O cell
feedback
complete pin-out stability
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Variable-grain logic cells provide high
performance and 100% utilization
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Comprehensive design tools include high
quality Verilog/VHDL synthesis
High Performance
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Input + logic cell + output total delays
under 6 ns
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Data path speeds over 400 MHz
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Counter speeds over 300 MHz
Advanced I/O Capabilities
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Interfaces with both 3.3 V and 5.0 V devices
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PCI compliant with 3.3 V and 5.0 V buses
for -1/-2/-3/-4 speed grades
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Full JTAG boundary scan
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I/O Cells with individually controlled
Registered Input Path and Output Enables
Total of 74 I/O Pins
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66 bidirectional input/output pins,
PCI-compliant for 5.0 V and 3.3 V buses for
-1/-2/-3/-4 speed grades
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Eight high-drive input/distributed
network pins
Figure 1: 96 pASIC 3 Logic Cells
© 2002 QuickLogic Corporation
www.quicklogic.com
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QL3004 pASIC 3 FPGA Data Sheet Rev D
Architecture Overview
The QL3004 is a 4,000 usable PLD gate member of the pASIC 3 family of FPGAs.
pASIC 3 FPGAs are fabricated on a 0.35
µm
four-layer metal process using QuickLogic
's
patented ViaLink
technology to provide a unique combination of high performance, high
density, low cost, and extreme ease-of-use.
The QL3004 contains 96 logic cells. With a maximum of 74 I/Os, the QL3004 is available
68-pin PLCC, 84-pin PLCC, and 100-pin TQFP packages.
Software support for the complete pASIC 3 family, including the QL3004, is available
through three basic packages. The turnkey QuickWorks
package provides the most
complete FPGA software solution from design entry to logic synthesis, to place and route,
to simulation. The QuickTools
TM
for Workstations package provides a solution for designers
who use Cadence
, Exemplar
TM
, Mentor
, Synopsys
, Synplicity
, Viewlogic
TM
, Aldec
TM
,
or other third-party tools for design entry, synthesis, or simulation.
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© 2002 QuickLogic Corporation
QL3004 pASIC 3 FPGA Data Sheet Rev D
Electrical Specifications
AC Characteristics at V
CC
= 3.3 V, TA = 25°C (K = 1.00)
To calculate delays, multiply the appropriate K factor from
Table 7
by the numbers provided
in
Table 1
through
Table 5
.
Table 1: Logic Cells
Symbol
Parameter
1
t
PD
t
SU
t
H
t
CLK
t
CWHI
t
CWLO
t
SET
t
RESET
t
SW
t
RW
Combinatorial Delay
Setup Time
b
Hold Time
Clock to Q Delay
Clock High Time
Clock Low Time
Set Delay
Reset Delay
Set Width
Reset Width
b
Propagation Delays (ns) Fanout
a
2
1.7
1.7
0.0
1.0
1.2
1.2
1.3
1.1
1.9
1.8
3
1.9
1.7
0.0
1.2
1.2
1.2
1.5
1.3
1.9
1.8
4
2.2
1.7
0.0
1.5
1.2
1.2
1.8
1.6
1.9
1.8
8
3.2
1.7
0.0
2.5
1.2
1.2
2.8
2.6
1.9
1.8
1.4
1.7
0.0
0.7
1.2
1.2
1.0
0.8
1.9
1.8
a. Stated timing for worst case Propagation Delay over process variation at V
CC
= 3.3 V and TA =
25
°
C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature set-
tings as specified in
Table 7
.
b. These limits are derived from a representative selection of the slowest paths through the
pASIC 3 logic cell including typical net delays. Worst case delay values for specific paths should
be determined from timing analysis of your particular design.
Table 2: Input-Only/Clock Cells
Symbol
Parameter
1
t
IN
t
INI
t
ISU
t
IH
t
lCLK
t
lRST
t
lESU
t
lEH
High Drive Input Delay
High Drive Input, Inverting Delay
Input Register Set-Up Time
Input Register Hold Time
Input Register Clock To Q
Input Register Reset Delay
Input Register clock Enable Set-Up Time
Input Register Clock Enable Hold Time
1.5
1.6
3.1
0.0
0.7
0.6
2.3
0.0
Propagation Delays (ns) Fanout
a
2
1.6
1.7
3.1
0.0
0.8
0.7
2.3
0.0
3
1.8
1.9
3.1
0.0
1.0
0.9
2.3
0.0
4
1.9
2.0
3.1
0.0
1.1
1.0
2.3
0.0
8
2.4
2.5
3.1
0.0
1.6
1.5
2.3
0.0
12
2.9
3.0
3.1
0.0
2.1
2.0
2.3
0.0
24
4.4
4.5
3.1
0.0
3.6
3.5
2.3
0.0
a. Stated timing for worst case Propagation Delay over process variation at V
CC
= 3.3 V and
TA = 25
°
C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and tempera-
ture settings as specified in
Table 7
.
© 2002 QuickLogic Corporation
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www.quicklogic.com
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QL3004 pASIC 3 FPGA Data Sheet Rev D
Table 3: Clock Cells
Symbol
Parameter
Propagation Delays (ns) Loads per Half Column
a
1
t
ACK
t
GCKP
t
GCKB
Array Clock Delay
Global Clock Pin Delay
Global Clock Buffer Delay
1.2
0.7
0.8
2
1.2
0.7
0.8
3
1.3
0.7
0.9
4
1.3
0.7
0.9
8
1.5
0.7
1.1
10
1.6
0.7
1.2
11
1.7
0.7
1.3
a. The array distributed networks consist of 40 half columns and the global distributed networks con-
sist of 44 half columns, each driven by an independent buffer. The number of half columns used
does not affect clock buffer delay. The array clock has up to eight loads per half column. The glo-
bal clock has up to 11 loads per half column.
Table 4: Input-Only I/O Cells
Symbol
Parameter
Propagation Delays (ns) Fanout
a
1
t
I/O
t
ISU
t
IH
t
lOCLK
t
lORST
t
lESU
t
lEH
Input Delay (bidirectional pad)
Input Register Set-Up Time
Input Register Hold Time
Input Register Clock To Q
Input Register Reset Delay
Input Register clock Enable Set-Up Time
Input Register Clock Enable Hold Time
1.3
3.1
0.0
0.7
0.6
2.3
0.0
2
1.6
3.1
0.0
1.0
0.9
2.3
0.0
3
1.8
3.1
0.0
1.2
1.1
2.3
0.0
4
2.1
3.1
0.0
1.5
1.4
2.3
0.0
8
3.1
3.1
0.0
2.5
2.4
2.3
0.0
10
3.6
3.1
0.0
3.0
2.9
2.3
0.0
a. Stated timing for worst case Propagation Delay over process variation at V
CC
= 3.3 V and
TA = 25
°
C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature
settings as specified in
Table 7
.
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© 2002 QuickLogic Corporation
QL3004 pASIC 3 FPGA Data Sheet Rev D
Table 5: Output-Only I/O Cells
Symbol
Parameter
30
t
OUTLH
t
OUTHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Output Delay Low to High
Output Delay High to Low
Output Delay Tri-state to High
Output Delay Tri-state to Low
Output Delay High to Tri-State
Output Delay Low to Tri-State
a
Propagation Delays (ns) Output Load
Capacitance (pF)
50
2.5
2.6
1.7
2.0
-
-
75
3.1
3.2
2.2
2.6
-
-
100
3.6
3.7
2.8
3.1
-
-
150
4.7
4.8
3.9
4.2
-
-
2.1
2.2
1.2
1.6
2.0
1.2
a. The loads presented in
Figure 2
are used for t
PXZ
:
t
PHZ
1ΚΩ
5 pF
1ΚΩ
t
PLZ
5 pF
Figure 2: Loads used for t
PXZ
© 2002 QuickLogic Corporation
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www.quicklogic.com
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