CD-700-KAF-GDB-40.000 datasheet, PDF

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CD-700-KAF-GDB-40.000: DescriptionPhase Locked Loop, CQCC16, 5 X 7.50 MM, 2 MM HEIGHT, HERMETIC SEALED, CERAMIC, SMD-16; CategoryAnalog mixed-signal IC The signal circuit; File Size123KB，14 Pages; ManufacturerVectron International, Inc.; Websitehttp://www.vectron.com/; Environmental Compliance

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CD-700-KAF-GDB-40.000 Overview

Phase Locked Loop, CQCC16, 5 X 7.50 MM, 2 MM HEIGHT, HERMETIC SEALED, CERAMIC, SMD-16

CD-700-KAF-GDB-40.000 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Vectron International, Inc.
Parts packaging code	SOIC
package instruction	QCCN, LCC16,.2X.3,40
Contacts	16
Reach Compliance Code	compliant
Analog Integrated Circuits - Other Types	PHASE LOCKED LOOP
JESD-30 code	R-CQCC-N16
JESD-609 code	e4
length	7.49 mm
Humidity sensitivity level	1
Number of functions	1
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QCCN
Encapsulate equivalent code	LCC16,.2X.3,40
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	260
power supply	5 V
Certification status	Not Qualified
Maximum seat height	2.13 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Gold (Au) - with Nickel (Ni) barrier
Terminal form	NO LEAD
Terminal pitch	1.02 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	5.08 mm

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CD-700

Complete VCXO Based Phase Lock Loop

Features

•

5 x 7.5 x 2 mm, smallest VCXO PLL available

•

Output Frequencies to 77.76 MHz

•

5.0 or 3.3 Vdc operation

•

Tri-State Output

•

Holdover on Loss of Signal Alarm

•

VCXO with CMOS outputs

•

0/70 or –40/85

°C

temperature range

•

Hermetically sealed ceramic SMD package

•

Product is compliant to RoHS directive

Applications

•

Frequency Translation

•

Clock Smoothing, Clock Switching

PHO OPN

(3)

(2)

OPOUT

(1)

(16)

LOSIN

(4)

•

NRZ Clock recovery

•

DSLAM, ADM, ATM, Aggregation, Optical

Switching/Routing, Base Station

DATAIN

(5)

CLKIN

(6)

VCXO

Phase

Detector

and LOS

OP-Amp

Optional

Divider

OUT1

(13)

•

Synchronous Ethernet

•

Low jitter PLL’s

OUT2

(11)

Description

The VI CD-700 is a user-configurable crystal

based PLL integrated circuit. It includes a digital

phase detector, op-amp, VCXO and additional

integrated functions for use in digital

synchronization applications. Loop filter software

is available as well SPICE models for circuit

simulation.

Tel: 1-88-VECTRON-1

•

Web:

www.vectron.com

Rev : 06Apr08

RCLK RDATA

(9)

(10)

OPP

(15)

GND

(7)

VDD

(14)

HIZ

(12)

Figure 1. CD-700 Block Diagram

Vectron International, 267 Lowell Rd, Hudson NH 03051-4916

Page 1 of 14

CD-700, VCXO Based PLL

CD-700 Theory of Operation

Phase Detector

The phase detector has two buffered inputs (DATAIN and CLKIN) which are designed to switch at

1.4 volts. DATAIN is designed to accept an NRZ data stream but may also be used for clock signals

which have a 50% duty cycle. CLKIN is connected to OUT1 or OUT2, or a divided version of one of these

outputs. CLKIN and DATAIN and are protected by ESD diodes and should not exceed the power supply

voltage or ground by more than a few hundred millivolts.

The phase detector is basically a latched flip flop/exclusive-or gate/differential amplifier filter design to

produce a DC signal proportional to the phase between the CLKIN and DATAIN signals (see Figure 4 for

a block diagram and Figure 5 for an open loop transfer curve). This will simplify the PLL design as the

designer does not have to filter narrow pulse signals to a DC level. Under locked conditions the rising

edge of CLKIN will be centered in the middle of the DATAIN signal (see Figure 6).

The phase detector gain is 0.53V/rad x data density for 5volt operation and 0.35V/rad x data density for

3.3 volt operation. Data density is equal to 1.0 for clock signals and is system dependent on coding and

design for NRZ signals, but 0.25 could be used as a starting point for data density.

The phase detector output is a DC signal for DATAIN frequencies greater than 1 MHz but produces

significant ripple when inputs are less than 200 kHz. Additional filtering is required for lower input

frequencies applications such as 8kHz (see Figures 8 and 9 as examples).

Under closed loop conditions the active filter has a blocking capacitor which provides a very high DC

gain, so under normal locked conditions and input frequencies >1 MHz, PHO will be about V

/2 and will

not vary significantly with changes in input frequency (within lock range). The control voltage (pin 16) will

vary according to the input frequency offset, but PHO will remain relatively constant.

Data In

(pin 5)

Clock In

(pin 6)

30 kΩ

20 kΩ

PHO

(pin 3)

Gain = V

/ 2π

Gain = 2 / 3

Figure 4. Simplified Phase Detector Block Diagram

Vectron International, 267 Lowell Rd, Hudson NH 03051-4916

Page 4 of 14

Tel: 1-88-VECTRON-1

•

Web:

www.vectron.com

Rev : 06Apr08

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