Document Revision History
Version History
Rev 0
Rev 1
Initial release
Updates to
Part 10, Specifications,
Table 10-1,
added maximum clamp current, per pin
Table 10-11,
clarified variation over temperature table and graph
Table 10-15,
added LIN slave timing
Added alternate pins to
Figure 11-1
and
Table 11-1.
Corrected bit selects in Timer Channel 3 Input (TC3_INP) bit 9,
Section 6.3.1.7,
clarified
Section 1.4.1,
and simplified notes in
Table 10-9,
Added clarification on sync inputs in
Section 1.4.1,
added voltage difference specification to
Table 10-1
and
Table 10-4,
deleted formula for Ambient Operating Temperature in
Table 10-4,
and a note for pin group 3, corrected
Table 8-1,
error in Port C peripheral function configuration,
updated notes in
Table 10-9.
Added RoHs and “pb-free” language to back cover.
Updates to
Section 10
Table 10-5,
corrected max values for ADC Input Current High and Low; corrected typ value for
pull-up disabled Digital Input Current Low (a)
Table 10-6,
corrected typ and added max values for Standby > Stop and Powerdown modes
Table 10-7,
corrected min value for Low-Voltage Interrupt for 3.3V
Table 10-11,
corrected typ and max values and units for PLL lock time
Table 10-12,
corrected typ values for Relaxation Oscillator output frequency and variation over
temperature (also increased temp range to 150 degreesC) and added variation over
temperature from 0—105 degreesC
Updated
Figure 10-5
Table 10-19,
updated max values for Integral Non-Linearity full input signal range, Negative
Differential Non-Linearity, ADC internal clock, Offset Voltage Internal Ref, Gain Error and Offset
Voltage External Ref; updated typ values for Negative Differential Non-Linearity, Offset Voltage
Internal Ref, Gain Error and Offset Voltage External Ref; added new min values and corrected
typ values for Signal-to-noise ratio, Total Harmonic Distortion, Spurious Free Dynamic Range,
Signal-to-noise plus distortion, Effective Number of Bits
Added details to Section 1. Clarified language in State During Reset column in
Table 2-3;
corrected flash data retention temperature in
Table 10-4;
moved input current high/low
toTable
10-19
and location of footnotes in
Table 10-5;
reorganized
Table 10-19;
clarified title of
Figure 10-1.
• In
Table 10-4,
added an entry for flash data retention with less than 100 program/erase
cycles (minimum 20 years).
• In
Table 10-6,
changed the device clock speed in STOP mode from 8MHz to 4MHz.
• In
Table 10-12,
changed the typical relaxation oscillator output frequency in Standby mode
from 400kHz to 200kHz.
Rev. 8
In
Table 10-19,
changed the maximum ADC internal clock frequency from 8MHz to 5.33MHz.
Description of Change
Rev 2
Rev 3
Rev 4
Rev 5
Rev 6
Rev. 7
56F8014 Technical Data, Rev. 11
2
Freescale Semiconductor
56F8014 General Description
• Up to 32 MIPS at 32MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 16KB Program Flash
• 4KB Unified Data/Program RAM
• One 5-channel PWM module
• Two 4-channel 12-bit ADCs
• One Serial Communication Interface (SCI) with LIN
slave functionality
• One Serial Peripheral Interface (SPI)
• One 16-bit Quad Timer
• One Inter-Integrated Circuit (I
2
C) Port
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• Integrated Power-On Reset and Low-Voltage Interrupt
Module
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 26 GPIO lines
• 32-pin LQFP Package
RESET
4
V
CAP
V
DD
V
SS_IO
2
V
DDA
V
SSA
5
PWM Outputs
PWM
or Timer Port
or GPIOA
Program Controller
and Hardware
Looping Unit
JTAG/EOnCE
Port or
GPIOD
Digital Reg
Analog Reg
16-Bit
56800E Core
Low-Voltage
Supervisor
Bit
Manipulation
Unit
Address
Generation Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
4
AD0
4
ADC
or
GPIOC
PAB
PDB
CDBR
CDBW
Memory
Program Memory
8K x 16 Flash
Unified Data /
Program RAM
4KB
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
R/W Control
AD1
System Bus
Control
IPBus Bridge (IPBB)
2
Timer or
GPIOB
SPI or I
2
C
or Timer
or GPIOB
4
SCI
or I
2
C
or GPIOB
2
COP/
Watchdog
Interrupt
Controller
System
Integration
Module
P
O
R
O
Clock
S
Generator*
C
*Includes On-Chip
Relaxation Oscillator
56F8014 Block Diagram
56F8014 Technical Data, Rev. 11
4
Freescale Semiconductor
56F8014 Data Sheet Table of Contents
Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.
1.2.
1.3.
1.4.
1.5.
1.6.
1.7.
1.8.
56F8014 Features . . . . . . . . . . . . . . . . . . . . 6
56F8014 Description. . . . . . . . . . . . . . . . . . . 8
Award-Winning Development Environment . 8
Architecture Block Diagram . . . . . . . . . . . . . 9
Synchronize ADC with PWM . . . . . . . . . . . . 9
Multiple Frequency PWM Output . . . . . . . . . 9
Product Documentation . . . . . . . . . . . . . . . 13
Data Sheet Conventions. . . . . . . . . . . . . . . 13
Part 7: Security Features . . . . . . . . . . . . . . .82
7.1. Operation with Security Enabled . . . . . . . . . 82
7.2. Flash Access Lock and Unlock Mechanisms 83
7.3. Product Analysis. . . . . . . . . . . . . . . . . . . . . . 84
Part 8: General Purpose Input/Output (GPIO)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
8.1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . 84
8.2. Configuration . . . . . . . . . . . . . . . . . . . . . . . . 84
8.3. Reset Values . . . . . . . . . . . . . . . . . . . . . . . . 86
Part 2: Signal/Connection Descriptions . . . 14
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2. 56F8014 Signal Pins . . . . . . . . . . . . . . . . . 18
Part 9: Joint Test Action Group (JTAG) . . .91
9.1. 56F8014 Information . . . . . . . . . . . . . . . . . . 91
Part 3: OCCS . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1.
3.2.
3.3.
3.4.
3.5.
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Modes . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . .
Pin Descriptions . . . . . . . . . . . . . . . . . . . . .
26
26
26
28
29
Part 10: Specifications . . . . . . . . . . . . . . . . .91
10.1. General Characteristics . . . . . . . . . . . . . . . 91
10.2. DC Electrical Characteristics . . . . . . . . . . . 95
10.3. AC Electrical Characteristics . . . . . . . . . . . 97
10.4. Flash Memory Characteristics . . . . . . . . . . 98
10.5. External Clock Operation Timing . . . . . . . . 99
10.6. Phase Locked Loop Timing . . . . . . . . . . . . 99
10.7. Relaxation Oscillator Timing. . . . . . . . . . . 100
10.8. Reset, Stop, Wait, Mode Select, and
Interrupt Timing . . . . . . . . . . . . . . 101
10.9. Serial Peripheral Interface (SPI) Timing . . 102
10.10. Quad Timer Timing. . . . . . . . . . . . . . . . . 105
10.11. Serial Communication Interface (SCI)
Timing . . . . . . . . . . . . . . . . . . . . . 107
10.12. Inter-Integrated Circuit Interface (I2C)
Timing . . . . . . . . . . . . . . . . . . . . . 108
10.13. JTAG Timing. . . . . . . . . . . . . . . . . . . . . . 109
10.14. Analog-to-Digital Converter (ADC)
Parameters . . . . . . . . . . . . . . . . . 111
10.15. Equivalent Circuit for ADC Inputs . . . . . . 112
10.16. Power Consumption . . . . . . . . . . . . . . . . 112
Part 4: Memory Map . . . . . . . . . . . . . . . . . . . 29
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Vector Table . . . . . . . . . . . . . . . . .
Program Map . . . . . . . . . . . . . . . . . . . . . . .
Data Map . . . . . . . . . . . . . . . . . . . . . . . . . .
EOnCE Memory Map . . . . . . . . . . . . . . . . .
Peripheral Memory Mapped Registers . . . .
29
29
31
32
32
33
Part 5: Interrupt Controller (ITCN) . . . . . . . . 43
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . .
Register Descriptions . . . . . . . . . . . . . . . . .
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
43
43
45
45
61
Part 6: System Integration Module (SIM) . . 62
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Descriptions . . . . . . . . . . . . . . . . .
Clock Generation Overview . . . . . . . . . . . .
Power-Down Modes . . . . . . . . . . . . . . . . . .
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .
62
62
64
77
77
79
81
82
Part 11: Packaging . . . . . . . . . . . . . . . . . . .115
11.1. 56F8014 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . . 115
Part 12: Design Considerations . . . . . . . . .118
12.1. Thermal Design Considerations . . . . . . . . 118
12.2. Electrical Design Considerations . . . . . . . 119
Part 13: Ordering Information . . . . . . . . . .121
Part 14: Appendix . . . . . . . . . . . . . . . . . . . .122
56F8014 Technical Data, Rev. 11
Freescale Semiconductor
5
Discrete Device
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