SD-14620 Series Data Sheet
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TWO-CHANNEL SYNCHRO/RESOLVER-
TO-DIGITAL (S/R-D) CONVERTERS
FEATURES
•
Synthesized Reference Option
•
1 Minute Accuracy Available
(“S” Option only)
•
Single +5 V Power Supply
•
10-, 12-, 14- or 16-Bit Programmable
Resolution
•
Small 54-Pin Ceramic Package
•
BIT Output
•
Velocity Output Replaces
Tachometer
•
High Reliability Single Chip
Monolithic
DESCRIPTION
The SD-14620 Series converters are small, low-cost, two-channel
hybrid Synchro- or Resolver-to-Digital converters based on a single-
chip monolithic. The SD-14620X“S” option offers synthesized refer-
ence circuitry to correct for phase shifts between the reference and
signal inputs. The two channels are independent but share the digital
output and +5 VDC power pins. The package is 54-pin ceramic, yet is
the size of a 28-pin DDIP.
Resolution programming allows selection of 10-, 12-, 14- or 16-bit
modes. This feature allows selection of either low-resolution for fast
tracking or higher resolution for higher accuracy.
The velocity outputs (VEL A, VEL B) of the SD-14620 Series, which can
be used to replace a tachometer, are ±4 V signals referenced to analog
ground.The SD-14620 Series also offers Built-In-Test outputs for each
channel (BIT-A, BIT-B). The converters are available with operating
temperature ranges of 0°C to +70°C, -40°C to +85°C and -55°C to
+125°C. MIL-PRF-38534 processing is available.
•
-55°C to +125°C Operating
Temperature Range
•
MIL-PRF-38534 Processing Available
APPLICATIONS
With its low-cost, small size, high accuracy and versatile performance,
the SD-14620 Series converters are ideal for use in modern high-per-
formance military, commercial and position control systems. Typical
applications include radar antenna positioning, motor control, robotics,
navigation and fire control systems.
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7771
All trademarks are the property of their respective owners.
©
1991, 1999 Data Device Corporation
TABLE 1. SD-14620 SERIES SPECIFICATIONS (EACH CHANNEL)
These specs apply over the rated power supply, temperature, and reference frequency ranges;
10% signal amplitude variation, and 10% harmonic distortion.
PARAMETER
RESOLUTION
ACCURACY
REPEATABILITY
DIFFERENTIAL LINEARITY
REFERENCE INPUT
Type
SD-14620
Voltage Range
Frequency
Input Impedance
single ended
differential
Common-Mode Range
SD-14620XS
Voltage Range
Frequency
Input Impedance
single ended
differential
Common-Mode Range
±Sig/Ref Phase Shift
SIGNAL INPUT
CHARACTERISTICS
90 V Synchro Input (L-L)
Zin line-to-line
Zin line-to-ground
Common-Mode Voltage
11.8 V Synchro Input (L-L)
Zin line-to-line
Zin line-to-ground
Common-Mode Voltage
11.8 V Resolver Input (L-L)
Zin line-to-line
Zin line-to-ground
Common-Mode Voltage
2 V Direct Input (L-L)
Voltage Range
Max. Voltage w/o Damage
Input Impedance
2 V Resolver Input (L-L)
Zin single ended
Zin differential
Common-Mode Voltage
DIGITAL INPUT/OUTPUT
Logic Type
INPUTS
UNIT
Bits
Min
LSB
LSB
VALUE
programmable 10, 12, 14, or 16
±1, ±2 or ±4, + 1 LSB (see TABLE 5)
1 max.
1 max.
(RH, RL)
Each Channel
differential
Vrms
Hz
2 & 11.8 V UNITS
2-35
360 - 5K
90 V UNIT
10-130
60 (47-5K)
400 (360-5K)
270K min.
540K min.
200, 300 transient
Ohm
Ohm
Vpeak
60K
120K
50, 100 transient
Vrms
Hz
2-35
1K - 5K
—
—
Ohm
Ohm
Vpeak
deg.
40K
80K
50, 100 transient
45 max
—
—
—
—
Ohm
Ohm
V
123K
80K
180 max.
Ohm
Ohm
V
52K
34K
30 max.
(same for “S” option)
140K
70K
30 max.
Ohm
Ohm
V
Vrms
V
Ohm
2 nom, 2.3 max.
25 cont, 100 pk transient
20 M || 10 pF min.
(“S” option only)
11K
22K
4.9 max.
TTL/CMOS compatible
Logic 0 = 0.8 V max.
Logic 1 = 2.0 V min.
Loading (per channel) =10
µA
max P.U. current source to
+5 V || 5 pF max.
CMOS transient protected.
Ohm
Ohm
V
Data Device Corporation
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SD-14620
U-8/12-0
TABLE 1. SD-14620 SERIES SPECIFICATIONS (CONTINUED)
PARAMETER
DIGITAL INPUT/OUTPUT
INPUTS (CONTINUED)
Each Channel
Resolution Control
Inhibit (lNH) (common)
Enable Bits 1 to 8 (EM)
Enable Bits 9 to 16 (EL)
OUTPUTS
Parallel Data (Note 3)
Each Channel
Built-In-Test
bits
UNIT
VALUE
Each Channel
See TABLE 2.
Logic 0 inhibits; Data stable within 0.5
µs
(Logic 1 is transparent)
Logic 0 enables; Data stable within 150 ns (Transparent mode)
Logic 1 = High Impedance, Data High Z within 100 ns
Common to all Channels
16 parallel lines; 2 bytes natural binary angle, positive logic. (see TABLE 3)
Each Channel
Logic 0 = BIT condition.
~ 100 LSBs positive error, ~ 250 LSBs negative error, with a filter of 500
µs
for LOS.
(LOS and LOR for “S” option)
TTL
50 PF +
Logic 0; 1 TTL load, 1.6 mA at 0.5 V max
Logic 1; 10 TTL loads,
-0.4 mA at 2.8 V min
Logic 0; 100mV max.
Logic 1; +5 V supply minus 100 mV min.
Each Channel
Positive for increasing angle
4.0 typ.
3.5 min.
10 typ.
20 max.
100 typ.
200 max.
1 typ.
2 max.
0.5 typ.
1.8 max.
2 typ.
3 max.
5 typ.
10 max.
15 typ.
30 max.
20 min.
0.125 min.
(1 typ.)
2 max.
-1.25 per +1 LSB error filtered (±3 LSB range).
+5
±5
+7
60 typ.
Drive Capability
CMOS
VELOCITY CHARACTERISTICS
(see Note 1)
Polarity
Voltage Range (Full Scale) (Note 3)
Scale Factor
Scale Factor TC
Reversal Error
Linearity
Linearity (90 V/60 Hz)
Zero Offset
Zero Offset TC
Load
Noise
DC ERROR (E)
POWER SUPPLIES
Nominal Voltage
Voltage Tolerance
Max. Voltage w/o Damage
Current
TEMPERATURE RANGE
Operating
-30X
-20X
-10X
Junction-to-Case (JC)
JC Thermal Rise
Junction Temperature
Storage
PHYSICAL
CHARACTERISTICS
Size
Weight
±V
±%
ppm/°C
±%
±%
±%
mV
µV/°C
KOhm
(Vp/V)%
V
V
%
V
mA
70 max.
°C
°C
°C
°C/W
°C
°C
°C
0 to +70
-40 to +85
-55 to +125
+55
+9 (see Note 2)
+140 max.
-65 to +150
in
(mm)
oz
(g)
1.50 x 0.78 x 0.21
(36.75 x 19.81 x 5.33)
0.66
(18.71)
NOTE:
1. Refer to TABLE 4 for full-scale tracking rate.
2. Applied to operating temperature
3. Dynamic accuracy may be degraded in high bandwidth system applications. See Theory of Operation section for details.
Data Device Corporation
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SD-14620
U-8/12-0
THEORY OF OPERATION
The SD-14620 Series of converters are based upon a single chip
CMOS custom monolithic. Using the latest technology, precision ana-
log circuitry is merged with digital logic to form a complete, high-per-
formance tracking Synchro/Resolver-to-Digital (S/D, R/D) converter.
GENERAL SET-UP CONSIDERATIONS
The following recommendations should be considered when
connecting the SD-14620 Series converters:
1) The +5 VDC power supply input is on pin 18. For performance
with the lowest amount of noise it is recommended that a
10
µF/10
VDC (or larger) tantalum filter capacitor be connect-
ed to ground (pin 19) near the converter package.
2) Direct inputs are referenced to Analog Ground (A GND).
Connections should be made as close to the converter pack-
age as possible to minimize noise. Channel A should be ref-
erenced to A GND-A (pin 5) and Channel B should be refer-
enced to A GND-B (pin 32).
3) A 47
µF/10
V tantalum filter capacitor must be added externally
from pin 52 (channel “A” filter point) to pin 19 (ground). In addi-
tion, a 47
µF/10
Vdc tantalum filter capacitor must be added
externally from pin 24 (channel “B” filter point) to pin 19 (ground).
CONVERTER OPERATION
FIGURE 1 is the Functional Block Diagram of the SD-14620
Series. The converter operates with a single +5 VDC power sup-
ply and each channel internally generates a negative voltage of
approximately 5 volts. These negative voltages are connected to
pin 52 (channel “A” filter point) and pin 24 (channel “B” filter
point) — see GENERAL SETUP CONSIDERATIONS.
The converter is made up of three main sections; an input front-
end, an error processor, and a digital interface. The converter
front-end differs for synchro, resolver and direct inputs. An elec-
tronic Scott-T is used for synchro inputs, a resolver conditioner
for resolver inputs, and a sine and cosine voltage follower for
direct inputs. These amplifiers feed the high accuracy Control
Transformer (CT). Its other input is the 16-bit digital angle
φ.
Its
output is an analog error angle, or difference angle, between the
two inputs. The CT performs the ratiometric trigonometric com-
putation of SINθCOSφ - COSθSINφ = SIN(θ -
φ)
using amplifiers,
switches, logic, and capacitors in precision ratios. The converter
accuracy is limited by the precision of the computing elements in
the CT. For enhanced accuracy, the CT in these converters use
capacitors in precision ratios, instead of the more conventional
precision resistor ratios. Capacitors that are used as computing
elements with op-amps are sampled at a high rate to eliminate
drift and the op-amp offsets.
The error processing is performed using the industry standard
technique for type II tracking R/D converters. The DC error is
integrated yielding a velocity voltage which in turn drives a volt-
age-controlled oscillator (VCO). This VCO is an incremental inte-
grator (constant-voltage input to position-rate output) that,
together with the velocity integrator, forms a type II servo feed-
back loop. A lead in the frequency response is introduced to sta-
bilize the loop and a lag at a higher frequency is introduced to
reduce the gain and ripple at the carrier frequency and above.
Dynamic accuracy may be degraded in applications with a high
system bandwidth. This dynamic accuracy error is usually not an
issue when using the device’s analog velocity output or position
output data in a control-loop because they are inherently filtered
due to comparatively low bandwidths in most applications.
SPECIAL FUNCTIONS
PROGRAMMABLE RESOLUTION
Resolution is controlled by pins 49 and 50 for channel A; pins 21
and 22 for channel B. The resolution can be changed during con-
verter operation, so the appropriate resolution and velocity
dynamics can be changed as needed. To insure that a race con-
dition does not exist between counting and changing the resolu-
tion, the resolution control is latched internally. Refer to TABLE 2
for Channel A and B resolution control.
TABLE 3. DIGITAL ANGLE OUTPUTS
BIT
1 (MSB ALL MODES)
2
3
4
5
6
7
8
9
10 (LSB 10-BIT MODE)
11
12 (LSB 12-BIT MODE)
13
14 (LSB 14-BIT MODE)
15
16 (LSB 16-BIT MODE)
DEG/BIT
180
90
45
22.5
11.25
5.625
2.813
1.406
0.7031
0.3516
0.1758
0.0879
0.0439
0.0220
0.0110
0.0055
MIN/BIT
10800
5400
2700
1350
675
337.5
168.75
84.38
42.19
21.09
10.55
5.27
2.64
1.32
0.66
0.33
TABLE 2. RESOLUTION CONTROL (A AND B)
RESOLUTION
10 bit
12 bit
14 bit
16 bit
B
0
0
1
1
A
0
1
0
1
Note: EM enables the MSB byte and EL enables the LSB byte.
Data Device Corporation
www.ddc-web.com
5
SD-14620
U-8/12-0
FPGA/CPLD
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