Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: DSP56F807VF80, DSP56F807VF80E
DSP56F807
Rev. 16
09/2007
56F807
Data Sheet
Preliminary Technical Data
freescale.com
56F800
16-bit Digital Signal Controllers
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: DSP56F807VF80, DSP56F807VF80E
Rev. 16
Version History
Document Revision History
Description of Change
Added revision history.
Added this text to footnote 2 in
Table 3-8:
“However, the high pulse width does not have to
be any particular percent of the low pulse width.”
56F807 General Description
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: DSP56F807VF80, DSP56F807VF80E
•
•
•
•
Up to 40 MIPS at 80MHz core frequency
DSP and MCU functionality in a unified,
C-efficient architecture
Hardware DO and REP loops
MCU-friendly instruction set supports both DSP
and controller functions: MAC, bit manipulation
unit, 14 addressing modes
60K
×
16-bit words (120KB) Program Flash
2K
×
16-bit words (4KB) Program RAM
8K
×
16-bit words (16KB) Data Flash
4K
×
16-bit words (8KB) Data RAM
2K
×
16-bit words (4KB) Boot Flash
Up to 64K
×
16- bit words (128KB) each of external
Program and Data memory
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Two 6 channel PWM Modules
Four 4 channel, 12-bit ADCs
Two Quadrature Decoders
CAN 2.0 B Module
Two Serial Communication Interfaces (SCIs)
Serial Peripheral Interface (SPI)
Up to four General Purpose Quad Timers
JTAG/OnCE
TM
port for debugging
14 Dedicated and 18 Shared GPIO lines
160-pin LQFP or 160 MAPBGA Packages
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6
3
4
6
PWM Outputs
Current Sense Inputs
Fault Inputs
PWM Outputs
Current Sense Inputs
Fault Inputs
A/D1
A/D2
A/D1
A/D2
ADCA
VREF
ADCB
VREF2
PWMA
RSTO
RESET
IRQA
EXTBOOT
IRQB
6
JTAG/
OnCE
Port
VPP
VCAPC V
DD
2
8
V
SS
10*
Digital Reg
V
DDA
3
V
SSA
3
Analog Reg
PWMB
3
4
4
4
4
4
Low Voltage
Supervisor
4
Quadrature
Decoder 0
/Quad Timer
Quadrature
Decoder 1
/Quad Timer B
Quad Timer C
Interrupt
Controller
Program Controller
and
Hardware Looping Unit
Address
Generation
Unit
Data ALU
16 x 16 + 36
→
36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Bit
Manipulation
Unit
4
2
4
2
2
Program Memory
61440 x 16 Flash
2048 x 16 SRAM
Boot Flash
2048 x 16 Flash
Data Memory
8192 x 16 Flash
4096 x 16 SRAM
•
PAB
•
•
PDB
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•
•
IPBB
CONTROLS
16
PLL
CLKO
Quad Timer D
/ Alt Func
CAN 2.0A/B
SCI0
or
GPIO
SCI1
or
GPIO
SPI
or
GPIO
Dedicated
GPIO
XDB2
CGDB
XAB1
XAB2
16-Bit
56800
Core
XTAL
Clock Gen
EXTAL
•
INTERRUPT
CONTROLS
16
COP/
Watchdog
COP RESET
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
2
4
14
Applica-
tion-Specific
Memory &
Peripherals
IPBus Bridge
(IPBB)
External
Bus
Interface
Unit
External
Address Bus
Switch
External
Data Bus
Switch
Bus
Control
A[00:05]
6
10
16
PS Select
DS Select
WR Enable
RD Enable
A[06:15] or
GPIO-E2:E3 &
GPIO-A0:A7
D[00:15]
*
includes TCS pin which is reserved for factory use and is tied to VSS
56F807 Block Diagram
56F807 Technical Data Technical Data, Rev. 16
Freescale Semiconductor
3
Part 1 Overview
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: DSP56F807VF80, DSP56F807VF80E
1.1 56F807 Features
1.1.1
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Processing Core
Efficient 16-bit 56800 family controller engine with dual Harvard architecture
As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
Single-cycle 16
×
16-bit parallel Multiplier-Accumulator (MAC)
Two 36-bit accumulators including extension bits
16-bit bidirectional barrel shifter
Parallel instruction set with unique processor addressing modes
Hardware DO and REP loops
Three internal address buses and one external address bus
Four internal data buses and one external data bus
Instruction set supports both DSP and controller functions
Controller style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/OnCE debug programming interface
1.1.2
•
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Memory
Harvard architecture permits as many as three simultaneous accesses to Program and Data memory
On-chip memory including a low-cost, high-volume Flash solution
— 60K
×
16-bit words of Program Flash
— 2K
×
16-bit words of Program RAM
— 8K
×
16-bit words of Data Flash
— 4K
×
16-bit words of Data RAM
— 2K
×
16-bit words of Boot Flash
•
Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states
— As much as 64K
×
16 bits of Data memory
— As much as 64K
×
16 bits of Program memory
1.1.3
•
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Peripheral Circuits for 56F807
Two Pulse Width Modulator modules each with six PWM outputs, three Current Sense inputs, and four
Fault inputs, fault tolerant design with dead time insertion, supports both center- and edge-aligned modes
Four 12-bit, Analog-to-Digital Converters (ADCs), which support four simultaneous conversions with
quad, 4-pin multiplexed inputs; ADC and PWM modules can be synchronized
Two Quadrature Decoders each with four inputs or two additional Quad Timers
56F807 Technical Data Technical Data, Rev. 16
4
Freescale Semiconductor
56F807 Description
•
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: DSP56F807VF80, DSP56F807VF80E
•
•
•
•
•
•
•
•
•
•
Two dedicated General Purpose Quad Timers totaling six pins: Timer C with two pins and Timer D with
four pins
CAN 2.0 B Module with 2-pin port for transmit and receive
Two Serial Communication Interfaces each with two pins (or four additional GPIO lines)
Serial Peripheral Interface (SPI) with configurable 4-pin port (or four additional GPIO lines)
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