Programmable Media Processors
Nexperia PNX1300 Series
Continuing a tradition of high-performance, low-cost
media processors, Philips Nexperia PNX1300 Series
delivers up to 200 MHz of power to a variety of
multimedia applications. While maintaining 100% pin
compatibility with their TM-1300 predecessors,
PNX1300 Series processors achieve over seven billion
operations per second in applications requiring
real-time processing of video, audio, graphics, and
communications datastreams.
Philips PNX1300 processors boost performance
through faster clock speeds and a faster main memory
interface than previous TM-1300 processors. An optional
lower-voltage CPU is also available, further improving
efficiency in power-constrained multimedia designs.
FEATURES
+
Processes audio, video, graphics and communications
datastreams on a single chip
+
Ideal for video-centric multimedia applications
+
Powerful, fine-grain parallel VLIW CPU
–
143-, 180-, or 200-MHz CPU achieves up to 7.7 BOPS
–
Optional lower-voltage 166-MHz CPU available
+
Versatile instruction set includes traditional microprocessor,
special multimedia SIMD, and IEEE floating-point operations
+
Comprehensive software development tools enable
multimedia application development entirely in the C/C++
programming languages
+
On-chip, independent, DMA-driven multimedia I/O and
coprocessing units offload the CPU
+
PCI/XIO host bus interface supports glueless interface
to PCI and eight-bit microcomputer peripherals including
ROM/Flash, EEPROM, 68K, and x86 devices
+
16-, 64-, 128-, and 256-Mbit SDRAM support up to 183 MHz
+
On-chip DVD playback authentication/descrambling
+
Application libraries available from Philips and third-party
suppliers provide solutions for MPEG-4 encode/decode,
MPEG-2 encode/decode, Dolby Digital (AC-3)
®
decode,
MP3 decode, and more
Philips PNX1300 processors are ideal building blocks for
devices required to process several types of multimedia
datastreams simultaneously, including the latest standards such
as MPEG-4, MPEG-2, H.263, MP3, and Dolby Digital
®
. With
ample computational power available to capture, compress, and
decompress many video and audio data formats in real time,
PNX1300s are well suited for a broad range of applications such
as Internet appliances, Web-cams, smart display pads, video and
screen phones, PVR, videoconferencing, video editing, video-
based security, Internet radios, DVD playback, wireless LAN
devices, and digital TV sets and set-top boxes. They also support
applications in a Java
TM
virtual machine environment.
Supported by the comprehensive TriMedia
TM
SDE software
development environment, PNX1300s are comparable in ease
of programmability to general-purpose processors. The SDE
enables multimedia application development entirely in the
C and C++ languages improving time-to-market and lowering
product development and maintenance costs.
Nexperia
PNX1300 Series
System-on-a-chip
multimedia engines
PNX1300 ARCHITECTURE
On a single chip, a PNX1300 incorporates a powerful CPU and
peripherals to accelerate processing of audio, video, graphics, control,
and communications datastreams.
Striking a perfect balance between cost and performance,
each PNX1300 Series processor leverages a powerful
C/C++-programmable very-long instruction word (VLIW)
TriMedia CPU to coordinate on-chip activities. To reap the
full benefit of the CPU, independent, on-chip, bus-mastering
DMA peripheral units manage and format datastream I/O
and accelerate processing of multimedia algorithms. A
sophisticated memory hierarchy manages internal I/O and
streamlines access to external memory. The result—
a single, low-cost, programmable system-on-a-chip uniquely
suited for both standalone and hosted multimedia products.
Hardware saved by eliminating complex scheduling logic reduces cost
and allows the integration of multimedia-specific features that enhance
the power of the CPU.
The PNX1300 CPU implements a 32-bit linear address space and
128 fully general-purpose 32-bit registers. Registers are not separated
into banks enabling any operation to use any register for any operand.
Powerful, DSP-like, C/C++-callable special operations—
In addition to traditional microprocessor operations and a full
complement of 32-bit, IEEE-compliant, floating point operations,
the PNX1300 instruction set includes special multimedia and DSP
operations (ops) to accelerate the performance of SIMD (single
instruction, multiple data) computations common in multimedia
applications. These special ops combine multiple simple operations
into a single VLIW instruction that can implement up to 12 traditional
microprocessor operations in a single clock cycle. When incorporated
into application source code, special ops dramatically improve perfor-
mance and increase the efficiency of a PNX1300’s parallel architecture.
Special multimedia ops are invoked with familiar function-call
syntax consistent with the C/C++ programming languages. They are
automatically scheduled to take full advantage of a PNX1300’s highly
parallel VLIW implementation. As with all other operations generated
by the TriMedia SDE’s VLIW compilation system, the scheduler takes
care of register allocation, operation packing, and flow analysis.
PROGRAMMABLE VLIW CPU
A PNX1300 CPU delivers top performance through an elegant
implementation of a fine-grain parallel VLIW architecture. Its five
issue-slot instruction length enables up to five simultaneous operations
to be scheduled into a single VLIW instruction. These operations can
simultaneously target any five of the CPU’s 27 pipelined functional
units within one clock cycle. Most common operations have their
results available in one clock cycle; more complex operations may
have multicycle latencies.
Unique to the TriMedia VLIW implementation, parallelism is optimized
at compile time by an innovative compilation system. No specialized
scheduling hardware is required to parallelize code during execution.
ON-CHIP I/O AND COPROCESSING UNITS
A PNX1300’s on-chip I/O and coprocessing units offload
the CPU enabling simultaneous processing of multiple
multimedia datastreams. Independent I/O units manage
datastream input, formatting, and output. Coprocessing
units accelerate algorithms common in multimedia
applications such as MPEG or digital audio decoding.
Intended for processing audio and video data, most units
can also be used in raw mode for capture or output of
any properly formatted data.
Video input—The
video input (VI) unit operates in one of several
modes to read data from an off-chip source into main memory. In
video mode, it accepts eight-bit parallel 4:2:2 YUV time-multiplexed
signals from any CCIR656-compliant device, such as a digital video
camera, digital video decoder, or devices connected through ECL-level
converters to the standard D1 parallel interface. After input, YUV
data is demultiplexed into separate Y, U, and V memory planes.
As needed, the VI unit can be programmed to perform on-the-fly 2X
horizontal resolution subsampling. For example, conversion of 720
pixels/line to 360 pixels/line reduces initial storage and bus bandwidth
requirements when low resolution video is desirable downstream.
After demux and optional subsampling, video data is written to
main memory.
In raw mode, the VI unit can receive raw application data with no
YUV processing requirements. For example, in some digital TV
applications, the VI unit receives an ATSC transport stream; demux
and other datastream processing are handled in software.
In message passing mode, the VI unit can receive messages (special
purpose raw data) from another PNX1300 video output port. This
is useful for control functions such as task synchronization between
processors in a multi-PNX1300 configuration.
Video output—In
video mode, the video output (VO) unit outputs
a digital YUV datastream to off-chip video subsystems such as a
digital video encoder chip, digital video recorder, or other CCIR656-
compatible device. The output signal is generated by gathering bytes
from the separate Y, U, and V planes stored in SDRAM.
While generating the multiplexed stream, the VO unit can perform
programmed processing tasks, including horizontal 2X upscaling to
convert from CIF/SIF to CCIR 601 resolution. For simultaneous
SPECIAL MULTIMEDIA OPERATIONS
The ume8uu operation, commonly used for motion estimation
in video compression, implements 11 simple operations in one
TriMedia special op.
display of graphics and live video, the VO unit can perform 129-level
alpha blending to generate sophisticated graphics overlays of arbitrary
size and position within the output image. Chroma keying, genlock
frame synchronization, programmable YUV output clipping are
also supported.
In raw mode, the VO unit can output raw data (not necessarily video)
that does not require video post processing, for example, an ATSC
bitstream. It can also be used in conjunction with the VI unit to pass
unidirection messages between PNX1300 Series processors.
The VO unit can either supply or receive video clock and/or synchro-
nizing signals from the external interface. Clock and timing registers
can be precisely controlled through programmable registers. Program-
mable interrupts and dual buffers facilitate continuous data streaming
by allowing the CPU to set up a buffer while another is being emptied
by the VO unit. Video clocks are available in all input or output modes.
Audio input and output—The
audio input (AI) and audio output
(AO) units provide all signals needed to read and write digital audio
datastreams to/from most high-quality, low-cost serial audio over-
sampling A/D and D/A converters and codecs. Both units connect
to off-chip stereo converters through flexible bit-serial interfaces.
The AI and AO units are highly programmable providing tremendous
flexibility in handling custom datastreams, adapting to custom protocols,
and upgrading to future audio standards. Driven by PNX1300, the
programmable audio sampling clock system supports a variety of
sample rates with fine-grain resolution enabling audio and video
synchronization in even the most complex multimedia applications.
The AI unit supports up to two channels of audio input. Mono and
16-bit stereo formats are supported. The AO unit outputs up to eight
channels using one external pin per channel and supports 16-bit and
32-bit stereo and mono formats. It can also be used to control highly
integrated PC codecs. Software support for decode and output of
Dolby Pro Logic
®
and Dolby Digital (AC-3) multichannel audio is
provided through optional application library modules.
SPDIF output—An
SPDIF out (SPDO) unit outputs a one-bit
high-speed serial datastream primarily for transmission of digital audio
data in SPDIF format to external audio equipment. The SPDO unit
supports two-channel linear PCM audio, one or more Dolby Digital
six-channel datastreams (embedded per Project 1937), or one or more
MPEG-1 or MPEG-2 audio streams (embedded per Project 1937).
It supports arbitrary, programmable sample rates independent of
and asynchronous to the sample rate of the AO unit.
Like the video and audio units, the SPDO unit supports a raw
(or transparent) mode. Since datastream content is entirely software
controlled, the SPDO unit can also be used as a general purpose
high-speed datastream output device such as a UART.
Image coprocessor—The
image coprocessor (ICP) unit off-loads
the CPU of cycle-consuming image processing tasks such as copying
an image from SDRAM to a host video frame buffer. The ICP unit can
operate as either a memory-to-memory or memory-to-PCI coprocessor
device. In both modes, it can perform horizontal or vertical image
filtering and scaling and can optionally perform YUV to RGB color-
space conversion for screen display (in memory-to-PCI mode).
The ICP also provides display support for live video in occluded
windows. The number and sizes of windows processed are limited only
by available bandwidth. The final resampled and converted images are
transmitted over the PCI bus to an optional off-chip graphics card/
frame buffer.
Variable length decoder—A
variable length decoder (VLD) unit
operates as a memory-to-memory coprocessor to decode Huffman-
encoded MPEG-1 and MPEG-2 video datastreams. After processing,
the VLD unit outputs a decoded stream optimized for MPEG-2
decompression software. This minimizes communications with the
CPU where other steps of MPEG processing are performed.
DVD descrambler—The
on-chip digital versatile disc (DVD)
descrambler unit provides DVD authentication and descrambling.
This enables developers to add low-cost, flexible DVD video playback
functions into multimedia products with minimal effort.
I
2
C interface—An
I
2
C interface provides an external I
2
C (or com-
patible interface) for use in hardware or software operation modes.
In hardware mode, it can connect to and control a variety of different
I
2
C multimedia devices allowing configuration and status inspection of
off-chip peripheral video devices such as digital encoders and decoders,
digital cameras, parallel I/O expanders, and more. I
2
C software mode
enables full software control of the I
2
C interface. The interface can also
be used to read the boot program from an off-chip EEPROM.
HOST-ASSISTED COPROCESSOR
MEMORY SYSTEM OVERVIEW
To meet the performance requirements of its target
applications while maintaining low cost, the PNX1300
memory subsystem couples substantial on-chip caches
with a glueless memory interface through a unique
internal bus or data highway.
Dedicated instruction and data cache—A
PNX1300 CPU is
supported by separate, dedicated on-chip data and instruction caches
that employ a variety of techniques to improve cache hit ratios and
thus CPU performance.
The dual-ported data cache allows two simultaneous accesses. It is
STANDALONE
non-blocking thus cache misses and CPU cache accesses can be handled
simultaneously. Early restart techniques reduce read-miss latency.
Background copyback reduces CPU stalls.
To reduce internal bus bandwidth requirements, instructions in
main memory and cache use a compressed format. Instructions are
decompressed in the instruction cache decompression unit before
being processed by the CPU.
To improve cache behavior and thus performance, both caches have
a locking mechanism. Cache coherency is maintained by software.
Glueless memory system interface—A
PNX1300 couples main
Nexperia PNX1300 Series media processors are designed for use as
the sole CPU in standalone systems and as a coprocessor in a hosted
or multiprocessor environment.
memory to substantial on-chip caches through a glueless main memory
interface (MMI). The MMI acts as the main memory controller and
programmable central arbiter that allocates memory bandwidth for
on-chip peripheral unit activities.
Flexible memory configurations enable a wide variety of PNX1300-
Synchronous serial interface—A
synchronous serial interface
(SSI) unit provides serial access for a variety of multimedia and
data communications applications. It contains the buffers and logic
necessary to interface with simple analog modem front ends. When
used with a V.34 application module, the SSI unit can provide fully
V.34-compliant modem capability. Alternatively, it can be connected
to an ISDN interface chip to provide advanced digital modem
capabilities.
Timers—A
PNX1300 provides four general purpose timers useful in
counting/timing events such as CPU clock cycles, data/instruction
breakpoints, cache tracing, audio/video clocks, and more. Three timers
are available to programmers, a fourth is reserved for system software.
PCI/XIO bus interface—A
PCI/XIO interface connects the CPU and
on-chip peripheral units to a PCI/XIO bus. In embedded applications
where a PNX1300 is the main processor, this interface enables it to
access off-chip devices implementing functions not provided on-chip.
In host-based applications, the interface connects the PNX1300 to a
standard PCI bus, allowing placement directly on the host mainboard
or a plug-in card. For low-cost standalone systems, XIO support allows
glueless connection of eight-bit x86 or 68K devices such as ROM,
Flash, EEPROM, UARTs, and more.
based systems to be built. The MMI supports 16-, 64-, 128-, and
256-Mbit SDRAMs and provides sufficient drive capacity for a
memory system up to 183-MHz comprising 8-MB (one 2Mx32),
16-MB (two 4Mx16 or two 2Mx32), or 32-MB (one 4Mx32 or two
8Mx16) memories. Programmable speed ratios allow SDRAM to have
a different clock speed than the PNX1300 CPU. PNX1300 can also
support a 16-bit memory interface to reduce cost at the board level.
Supported memory configurations include 8-, 16-, and 32-MB using
4Mx16, 8Mx16, or 16Mx16 SDRAM devices, respectively.
HIGH-SPEED INTERNAL BUS (DATA HIGHWAY)
The PNX1300 CPU and processing units access external SDRAM
through the on-chip internal bus or data highway comprising separate
32-bit address and data buses. Handled by the MMI, programmable
bus arbitration enables the data highway to maintain real-time
responsiveness in a variety of applications.
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