INTEGRATED CIRCUITS
DATA SHEET
PCF8833
STN RGB - 132
×
132
×
3 driver
Objective specification
2003 Feb 14
Philips Semiconductors
Objective specification
STN RGB - 132
×
132
×
3 driver
CONTENTS
1
2
3
4
5
6
6.1
6.2
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
8
8.1
9
9.1
9.2
FEATURES
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
INSTRUCTIONS
Exit commands
Function set
FUNCTIONAL DESCRIPTION
MPU interfaces
Display data RAM and access arbiter
Command decoder
Grey scale controller
Timing generator
Oscillator
Reset
LCD voltage generator and bias level generator
Column drivers, data processing and data
latches
Row drivers
PARALLEL INTERFACE
8080-series 8-bit parallel interface
SERIAL INTERFACE
Write mode
Read mode
10
11
12
13
14
14.1
15
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
15.9
16
17
18
19
20
21
LIMITING VALUES
HANDLING
DC CHARACTERISTICS
AC CHARACTERISTICS
PCF8833
APPLICATION INFORMATION
Supply and capacitor connection configuration
MODULE MAKER PROGRAMMING
V
LCD
calibration
Factory defaults
Seal bit
OTP architecture
Interface commands
Suggestion on how to calibrate V
LCD2
using
MMVOP
Example of filling the shift register
Programming flow
Programming specification
INTERNAL PROTECTION CIRCUITS
BONDING PAD INFORMATION
TRAY INFORMATION
DATA SHEET STATUS
DEFINITIONS
DISCLAIMERS
2003 Feb 14
2
Philips Semiconductors
Objective specification
STN RGB - 132
×
132
×
3 driver
1
FEATURES
PCF8833
•
Analog supply voltage range for V
LCD
generation V
DD2
to V
SS2
:
– 2.4 to 4.5 V.
•
Analog supply voltage range for reference voltage
generation V
DD3
to V
SS1
:
– 2.4 to 3.5 V.
•
Display supply voltage range V
LCD
to V
SS1
:
– 3.8 to 20 V.
•
Low power consumption; suitable for battery operated
systems
•
CMOS compatible inputs
•
Manufactured in silicon gate CMOS process
•
Optimized layout for COF, Chip On Glass (COG) and
Transformer Coupled Plasma (TCP) assembly.
2
GENERAL DESCRIPTION
•
Single chip LCD controller and driver
•
132 rows and 396 column outputs (132
×
RGB)
•
Low cross talk by Frame Rate Control (FRC)
•
4 kbyte colours (RGB) = 4 : 4 : 4 mode
•
256 colours (RGB) = 3 : 3 : 2 mode using the 209 kbit
RAM and a Look-Up Table (LUT)
•
65 kbyte colours (RGB) = 5 : 6 : 5 mode using the
209 kbit RAM with dithering
•
8 colours Power-save mode
•
Display data RAM 132
×
132 (RGB) (4 kbyte colour)
•
Interfaces:
– 3-line serial interface
– 8-bit 8080 Intel CPU interface.
•
Display features:
– Area scrolling
– 32-line partial Display mode
– Software programmable colour depth mode
– N-line inversion for low cross talk.
•
On-chip:
– Oscillator for display system, requires no external
components (external clock also possible)
– Generation of V
LCD
– Segmented temperature compensation of V
LCD
and
frame frequency.
•
Logic supply voltage range V
DD1
to V
SS1
:
– 1.5 to 3.3 V.
3
ORDERING INFORMATION
The PCF8833 is a single chip low power CMOS LCD
controller driver, designed to drive colour Super-Twisted
Nematic (STN) displays of 132 rows and 132 RGB
columns. All necessary functions for the display are
provided in a single chip, including display RAM which has
a capacity of 209 kbit (132
×
12-bit
×
132). The PCF8833
uses the Multiple Row Addressing (MRA) driving
technique in order to achieve the best optical performance
at the lowest power consumption. The PCF8833 offers
2 types of microcontroller interfaces namely the
8080 system interface and the 3-line serial interface.
PACKAGE
TYPE NUMBER
NAME
PCF8833U/2DA/1
−
chip with bumps in tray
DESCRIPTION
VERSION
−
2003 Feb 14
3
Philips Semiconductors
Objective specification
STN RGB - 132
×
132
×
3 driver
4
BLOCK DIAGRAM
PCF8833
handbook, full pagewidth
C0 to C395
34 to 429
R0 to R131
2 to 33, 430 to 461,
464 to 495, 733 to 768
VLCDIN2
V2H
V1H
VC
V1L
V2L
VLCDSENSE
VLCDOUT1
VLCDIN1
VLCDOUT2
VDD2
C1+
C1−
C2+
C2−
C3+
C3−
C4+
C4−
C5+
C5−
VSS2
VOTP(gate)
VOTP(drain)
VDD3
VDD1
VSS1
713, 719
731, 732
729, 730
724 to 728
722, 723
720, 721
LCD BIAS
LEVEL
GENERATOR
COLUMN DRIVERS
ROW
DRIVERS
712
674 to 683
684 to 690
703 to 711
530 to 539
626 to 631
632 to 637
638 to 643
644 to 649
650 to 655
656 to 661
662 to 667
668 to 673
691 to 696
697 to 702
508 to 517
565 to 572
557 to 564
DATA PROCESSING
ORTHOGONAL
FUNCTION
GENERATOR
DATA LATCHES
RESET
LCD
VOLTAGE
GENERATOR
496
RES
OSCILLATOR
DISPLAY DATA RAM
132
×
132
×
12-bits
555
OSC
TIMING
GENERATOR
578
577
576
575
T1
T2
T3
T4
T5
T6
T7
GREYSCALE
CONTROLLER
X AND Y RAM WRITE
ADDRESS COUNTER
DISPLAY ADDRESS
READ COUNTER
COMMAND
DECODER
ARBITER
525 to 529
519 to 524
498 to 507
574
573
625
PCF8833
256/64 KBYTES
TO 4 KBYTES
COLOUR
MAPPING
579, 624
256
COLOUR
LUT
MPU INTERFACES
556
518 549 551 550 552 553 554 548 547 545 543 541 546 544 542 540 497
CS/SCE
RD
WR
PS0
PS1
PS2
D0/SDIN
D1
D2
D3
D4
D5
D6
D7
TE
MGU910
VDD(tieoff)
VSS(tieoff)
D/C/SCLK
SDOUT
Fig.1 Block diagram.
2003 Feb 14
4
Philips Semiconductors
Objective specification
STN RGB - 132
×
132
×
3 driver
5
PINNING
SYMBOL
R95 to R64
C0 to C395
R0 to R31
R63 to R32
RES
TE
V
SS1
V
SS2
CS/SCE
V
DD1
V
DD3
V
DD2
PAD
2 to 33
34 to 429
430 to 461
464 to 495
496
497
498 to 507
508 to 517
518
519 to 524
525 to 529
530 to 539
TYPE
O
O
O
O
I
O/I
PS
PS
I
PS
PS
PS
LCD row driver outputs
LCD column driver outputs
LCD row driver outputs
LCD row driver outputs
DESCRIPTION
PCF8833
external reset; this signal will reset the device and must be applied to properly
initialize the chip (active LOW)
tearing line (in Normal mode it is always an output)
system ground
system ground
chip select parallel interface or serial chip enable (active LOW)
logic supply voltage
V
DD2
and V
DD3
are the supply voltage pins for the internal voltage generator
including the temperature compensation circuits; V
DD2
and V
DD3
can be
connected together but in this case care must be taken to respect the supply
voltage range (see Chapter 13); V
DD1
is used as the supply for the rest of the
chip. V
DD1
can be connected together with V
DD2
and V
DD3
but in this case care
must also be taken to respect the supply voltage range; see Chapter 13. V
DD2
and V
DD3
must not be applied before V
DD1.
If the internal voltage generator is not used, pins V
DD2
and V
DD3
must be
connected to V
DD1
.
D7
D3
D6
D2
D5
D1
D4
D0/SDIN
SDOUT
D/C/SCLK
WR
RD
PS0
PS1
PS2
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
I
I
I
I
8-bit parallel data; in Serial mode tie to V
SS1
or V
DD1
8-bit parallel data; in Serial mode tie to V
SS1
or V
DD1
8-bit parallel data; in Serial mode tie to V
SS1
or V
DD1
8-bit parallel data; in Serial mode tie to V
SS1
or V
DD1
8-bit parallel data; in Serial mode tie to V
SS1
or V
DD1
8-bit parallel data; in Serial mode tie to V
SS1
or V
DD1
8-bit parallel data; in Serial mode tie to V
SS1
or V
DD1
8-bit parallel data or serial data input
serial data output; in Parallel mode tie to V
DD1
, V
SS1
or D0
data/command indicator parallel interface or serial clock
write clock parallel interface; in Serial mode tie to V
DD1
(active LOW)
read clock parallel interface; in Serial mode tie to V
DD1
(active LOW)
set serial or parallel interface mode PS1 and PS2 must tied to either V
SS1
or
V
DD1
set serial or parallel interface mode PS1 and PS2 must tied to either V
SS1
or
V
DD1
set serial or parallel interface mode PS1 and PS2 must tied to either V
SS1
or
V
DD1
2003 Feb 14
5
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