CAT28C16ALA-90T datasheet, PDF

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CAT28C16ALA-90T: Description16K-Bit CMOS PARALLEL E2PROM; Categorystorage storage; File Size124KB，10 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn

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CAT28C16ALA-90T Overview

16K-Bit CMOS PARALLEL E2PROM

CAT28C16ALA-90T Parametric

Parameter Name	Attribute value
Maker	ON Semiconductor
package instruction	DIP, DIP24,.6
Reach Compliance Code	compli
ECCN code	EAR99
Maximum access time	90 ns
command user interface	NO
Data polling	YES
Data retention time - minimum	100
Durability	100000 Write/Erase Cycles
JESD-30 code	R-PDIP-T24
length	31.875 mm
memory density	16384 bi
Memory IC Type	EEPROM
memory width	8
Number of functions	1
Number of terminals	24
word count	2048 words
character code	2000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	105 °C
Minimum operating temperature	-40 °C
organize	2KX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP24,.6
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Maximum seat height	6.35 mm
Maximum standby current	0.0001 A
Maximum slew rate	0.035 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
switch bit	NO
width	15.24 mm
Maximum write cycle time (tWC)	5 ms

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CAT28C16A

16 kb CMOS Parallel

EEPROM

Description

The CAT28C16A is a fast, low power, 5V−only CMOS Parallel

EEPROM organized as 2K x 8−bits. It requires a simple interface for

in−system programming. On−chip address and data latches,

self−timed write cycle with auto−clear and V

power up/down write

protection eliminate additional timing and protection hardware. DATA

Polling signals the start and end of the self−timed write cycle.

Additionally, the CAT28C16A features hardware write protection.

The CAT28C16A is manufactured using ON Semiconductor’s

advanced CMOS floating gate technology. It is designed to endure

100,000 program/erase cycles and has a data retention of 100 years.

The device is available in JEDEC approved 24−pin DIP and SOIC or

32−pin PLCC packages.

Features

http://onsemi.com

SOIC−24

J, K, W, X SUFFIX

CASE 751BK

•

Fast Read Access Times: 90 ns, 120 ns, 200 ns

•

Low Power CMOS Dissipation:

•

– Active: 25 mA Max.

– Standby: 100

Max.

Simple Write Operation:

– On−chip Address and Data Latches

– Self−timed Write Cycle with Auto−clear

Fast Write Cycle Time: 10 ms Max

End of Write Detection: DATA Polling

Hardware Write Protection

CMOS and TTL Compatible I/O

100,000 Program/Erase Cycles

100 Year Data Retention

Commercial, Industrial and Automotive Temperature Ranges

PIN CONFIGURATION

PDIP−24

L SUFFIX

CASE 646AD

PLCC−32

N, G SUFFIX

CASE 776AK

PIN FUNCTION

Pin Name

−A

I/O

−I/O

Function

Address Inputs

Data Inputs/Outputs

Chip Enable

Output Enable

Write Enable

5 V Supply

Ground

No Connect

DIP Package (L)

SOIC Package (J, K, W, X)

I/O

PLCC Package (N, G)

ORDERING INFORMATION

I/O

See detailed ordering and shipping information in the package

dimensions section on page 10 of this data sheet.

4 3 2 1 32 31 30

TOP VIEW

14 15 16 17 18 19 20

I/O

Semiconductor Components Industries, LLC, 2009

October, 2009

−

Rev. 6

Publication Order Number:

CAT28C16A/D

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