a
FEATURES
All-In-One Synchronous Buck Driver
Bootstrapped High-Side Drive
One PWM Signal Generates Both Drives
Anticross-Conduction Protection Circuitry
Pulse-by-Pulse Disable Control
IN
VCC
Dual Bootstrapped
MOSFET Driver
ADP3414
FUNCTIONAL BLOCK DIAGRAM
BST
DRVH
OVERLAP
PROTECTION
CIRCUIT
APPLICATIONS
Mobile Computing CPU Core Power Converters
Multiphase Desktop CPU Supplies
Single-Supply Synchronous Buck Converters
Standard-to-Synchronous Converter Adaptations
SW
DRVL
ADP3414
PGND
GENERAL DESCRIPTION
The ADP3414 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs which are the two switches in a
nonisolated synchronous buck power converter. Each of the
drivers is capable of driving a 3000 pF load with a 20 ns propa-
gation delay and a 30 ns transition time. One of the drivers can
be bootstrapped, and is designed to handle the high-voltage
slew rate associated with “floating” high-side gate drivers.
The ADP3414 includes overlapping drive protection (ODP)
to prevent shoot-through current in the external MOSFETs.
The ADP3414 is specified over the commercial temperature
range of 0°C to 70°C and is available in an 8-lead SOIC package.
7V
D1
12V
VCC
ADP3414
BST
C
BST
DRVH
IN
Q1
SW
DELAY
+1V
DRVL
1V
PGND
Q2
Figure 1. General Application Circuit
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
ADP3414–SPECIFICATIONS
1
(T = 0 C to 70 C, VCC = 7 V, BST = 4 V to 26 V, unless otherwise noted.)
A
Parameter
SUPPLY
Supply Voltage Range
Quiescent Current
PWM INPUT
Input Voltage High
2
Input Voltage Low
2
HIGH-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Transition Times
3
(See Figure 2)
Propagation Delay
3, 4
(See Figure 2)
LOW-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Transition Times
3
(See Figure 2)
Propagation Delay
3, 4
(See Figure 2)
Symbol
VCC
ICC
Q
Conditions
Min
4.15
Typ
Max
7.5
2
Unit
V
mA
V
V
Ω
Ω
Ω
Ω
ns
ns
ns
ns
Ω
Ω
Ω
Ω
ns
ns
ns
ns
1
2.3
0.8
V
BST
– V
SW
= 5 V
V
BST
– V
SW
= 7 V
V
BST
– V
SW
= 5 V
V
BST
– V
SW
= 7 V
V
BST
– V
SW
= 7 V, C
LOAD
= 3 nF
V
BST
– V
SW
= 7 V, C
LOAD
= 3 nF
V
BST
– V
SW
= 7 V
V
BST
– V
SW
= 7 V
VCC = 5 V
VCC = 7 V
VCC = 5 V
VCC = 7 V
VCC = 7 V, C
LOAD
= 3 nF
VCC = 7 V, C
LOAD
= 3 nF
VCC = 7 V
VCC = 7 V
3.0
2.0
1.25
1.0
36
20
65
21
3.0
2.0
1.5
1.0
27
19
30
15
5.0
3.5
2.5
2.5
47
30
86
32
5.0
3.5
3.0
2.5
35
26
35
25
tr
DRVH
tf
DRVH
tpdh
DRVH
tpdl
DRVH
tr
DRVL
tf
DRVL
tpdh
DRVL
tpdl
DRVL
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2
Logic inputs meet typical CMOS I/O conditions for source/sink current (~1
µA).
3
AC specifications are guaranteed by characterization, but not production tested.
4
For propagation delays, “tpdh” refers to the specified signal going high; “tpdl” refers to it going low.
Specifications subject to change without notice.
–2–
REV. 0
ADP3414
ABSOLUTE MAXIMUM RATINGS*
ORDERING GUIDE
Model
Temperature Package
Range
Description
8-Lead Standard
Small Outline (SOIC)
Package
Option
SO-8
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +8 V
BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V
BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +8 V
SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5.0 V to +25 V
IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Operating Ambient Temperature Range . . . . . . . 0°C to 70°C
Operating Junction Temperature Range . . . . . . 0°C to 125°C
θ
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155°C/W
θ
JC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
*This
is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged. Unless otherwise specified, all voltages are referenced
to PGND.
ADP3414JR 0°C to 70°C
PIN CONFIGURATION
BST
IN
NC
VCC
1
2
3
4
8
DRVH
SW
PGND
DRVL
ADP3414
TOP VIEW
(Not To Scale)
7
6
5
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Pin
1
Mnemonic
BST
Function
Floating Bootstrap Supply for the Upper MOSFET. A capacitor connected between BST and SW pins
holds this bootstrapped voltage for the high-side MOSFET as it is switched. The capacitor should be
chosen between 100 nF and 1 F.
TTL-level Input Signal, which has primary control of the drive outputs.
No Connection.
Input Supply. This pin should be bypassed to PGND with ~1
µF
ceramic capacitor.
Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
Power Ground. Should be closely connected to the source of the lower MOSFET.
This pin is connected to the buck-switching node, close to the upper MOSFET’s source. It is the floating
return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn-
on of the lower MOSFET until the voltage is below ~1 V. Thus, according to operating conditions, the
high-low transition delay is determined at this pin.
Buck Drive. Output drive for the upper (buck) MOSFET.
2
3
4
5
6
7
IN
NC
VCC
DRVL
PGND
SW
8
DRVH
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3414 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
ADP3414
IN
tpdl
DRVL
DRVL
tf
DRVL
tpdl
DRVH
tr
DRVL
tf
DRVH
tpdh
DRVH
tr
DRVH
DRVH-SW
V
TH
V
TH
tpdh
DRVL
SW
1V
Figure 2. Nonoverlap Timing Diagram (Timing Is Referenced to the 90% and 10% Points Unless Otherwise Noted)
–4–
REV. 0
Typical Performance Characteristics– ADP3414
50
T
DRVH
5V/DIV
R3
T
A
= 25 C
VCC = 5V
T
T
A
= 25 C
VCC = 5V
R3
DRVL
2V/DIV
TIME – ns
C
LOAD
= 3nF
DRVH
5V/DIV
45
DRVH @ VCC = 5V
40
DRVH @ VCC = 7V
DRVL @ VCC = 5V
IN
R2
R1
2V/DIV
40ns/DIV
DRVL
5V/DIV
R2
R1
35
IN
2V/DIV
40ns/DIV
30
25
DRVL @ VCC = 7V
20
0
25
50
75
100
JUNCTION TEMPERATURE – C
125
TPC 1. DRVH Fall and DRVL Rise
Times
TPC 2. DRVL Fall and DRVH Rise
Times
TPC 3. DRVH and DRVL Rise Times
vs. Temperature
35
DRVL @ VCC = 7V
30
25
TIME – ns
55
50
DRVH @ VCC = 5V
DRVL @ VCC = 5V
37
32
DRVL @ VCC = 7V
27
45
40
20
15
10
DRVH @ VCC = 7V
DRVH @ VCC = 5V
TIME – ns
DRVH @ VCC = 7V
35
30
25
20
DRVL @ VCC = 5V
DRVL @ VCC = 7V
TIME – ns
22
17
DRVH @ VCC = 5V
DRVH @ VCC = 7V
DRVL @ VCC = 5V
5
0
12
15
0
25
50
75
100
JUNCTION TEMPERATURE – C
125
10
1.0
2.0
3.0
4.0
LOAD CAPACITANCE – nF
5.0
7
1.0
1.5
2.0 2.5 3.0 3.5 4.0 4.5
LOAD CAPACITANCE – nF
5.0
TPC 4. DRVH and DRVL Fall Times
vs. Temperature
TPC 5. DRVH and DRVL Rise Times
vs. Load Capacitance
TPC 6. DRVH and DRVL Fall Times
vs. Load Capacitance
35
30
SUPPLY CURRENT – mA
8.5
T
A
= 25 C
C
LOAD
= 3nF
SUPPLY CURRENT – mA
8.0
VCC = 7V
7.5
7.0
6.5
6.0
VCC = 5V
5.5
5.0
C
LOAD
= 3nF
f
IN
= 250kHz
25
VCC = 7V
20
15
10
5
0
VCC = 5V
0
200
400 600 800 1000 1200 1400
IN FREQUENCY – kHz
0
100
25
50
75
JUNCTION TEMPERATURE – C
125
TPC 7. Supply Current vs.
Frequency
TPC 8. Supply Current vs.
Temperature
REV. 0
–5–
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