MCM64E836FC3.3 datasheet, PDF - EEWORLD Datasheet

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MCM64E836FC3.3: Description256KX36 DDR SRAM, PBGA153, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, FLIP CHIP, BGA-153; Categorystorage storage; File Size425KB，22 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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MCM64E836FC3.3 Overview

256KX36 DDR SRAM, PBGA153, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, FLIP CHIP, BGA-153

MCM64E836FC3.3 Parametric

Parameter Name	Attribute value
Maker	NXP
Parts packaging code	BGA
package instruction	BGA,
Contacts	153
Reach Compliance Code	unknown
ECCN code	3A991
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B153
length	22 mm
memory density	9437184 bit
Memory IC Type	DDR SRAM
memory width	36
Number of functions	1
Number of terminals	153
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX36
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	2.77 mm
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	14 mm

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MOTOROLA

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MCM64E918/D

8MB Double Data Rate HSTL I/O

Fast SRAM

MCM64E918

MCM64E836

Freescale Semiconductor, Inc...

•

Single 2.5 V

5% Power Supply

(DDR) Burst Read and

•

Single Data Rate (SDR) and Double Data Rate

Write

•

Pin Selectable Linear or Interleaved Burst Order

•

Four Tick Burst with Automatic

Wrap–Around

•

Differential Clock Inputs

•

Active High and Active

Echo Clock Outputs

Low

•

1.8 V Expanded HSTL — I/O (JEDEC Standard JESD8–6 Class I

Compatible)

•

1.8 V Expanded HSTL — Compatible Programmable Impedance Output

Drivers

•

Pipelined (Register to Register) Synchronous Operation

•

Boundary Scan (JTAG) IEEE 1149.1 Compatible

•

Stop Clock Functionality Supported

•

Optional x18 or x36 Organization

•

MCM64E918/MCM64E836–3.0 = 3.0 ns Clock Cycle Time

MCM64E918/MCM64E836–3.3 = 3.3 ns Clock Cycle Time

MCM64E918/MCM64E836–4.0 = 4.0 ns Clock Cycle Time

•

9 x 17 (153) Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Flipped Chip

Plastic Ball Grid Array (PBGA) package

The MCM64E918/MCM64E836 are 8M–bit pipelined burst synchronous late

write fast static RAMs designed to provide very high data bandwidth in secondary

cache applications. The MCM64E918 (organized as 512K words by 18 bits wide)

and the MCM64E836 (organized as 256K words by 36 bits wide) are fabricated

in Motorola’s high performance silicon gate MOS technology.

The differential clock (CK) inputs control the timing of read/write operations of

the RAM. At the rising edge of CK, all addresses and burst control inputs are reg-

istered. An internal buffer and special logic enables the memory to accept write

data on the rising or rising and falling edges of the clock, a cycle following address

and control signals. Read data is driven on the rising or rising and falling edges

of the CK clock and is referenced to echo clock (CQ and CQ) outputs.

The MCM64E918/MCM64E836 have HSTL inputs and outputs. The adjust-

able input trip–point (V

ref

) and output power supply voltage (V

DDQ

) gives

the system designer greater flexibility in optimizing system performance.

The impedance of the output buffers is programmable, allowing the outputs to

match the impedance of the circuit traces, which reduces

signal reflections.

FC PACKAGE

FLIPPED CHIP PBGA

CASE 1107C–03

REV2

7/2/01



Motorola, Inc. 2001

MOTOROLA FAST SRAM

For More Information On This Product,

Go to: www.freescale.com

MCM64E918•MCM64E836

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