MT58LC128K18C5LG-11 datasheet, PDF

Datasheet> All Categories > storage> storage> MT58LC128K18C5LG-11

MT58LC128K18C5LG-11: DescriptionCache SRAM, 128KX18, 6ns, CMOS, PQFP100, MS-026, TQFP-100; Categorystorage storage; File Size241KB，18 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/

Download Datasheet Parametric Compare View All

MT58LC128K18C5LG-11 Overview

Cache SRAM, 128KX18, 6ns, CMOS, PQFP100, MS-026, TQFP-100

MT58LC128K18C5LG-11 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Micron Technology
Parts packaging code	QFP
package instruction	MS-026, TQFP-100
Contacts	100
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	6 ns
Other features	BURST CONTROL; SELF TIMED WRITE CYCLE; REGISTER ADDRESS; BYTE WRITE CONTROL; AUTOMATIC POWER DOWN
Maximum clock frequency (fCLK)	90 MHz
I/O type	COMMON
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	2359296 bit
Memory IC Type	CACHE SRAM
memory width	18
Number of functions	1
Number of terminals	100
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP100,.63X.87
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	235
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.01 A
Minimum standby current	3.14 V
Maximum slew rate	0.25 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm

Preview

Download Datasheet

View All

OBSOLETE

128K x 18, 64K x 32/36

3.3V I/O, PIPELINED, DCD SYNCBURST SRAM

SYNCBURST

SRAM

FEATURES

•

Fast access times: 4.5ns, 5ns, 6ns and 7ns

Fast OE# access times: 4.5ns and 5ns

Single +3.3V +0.3V/-0.165V power supply (V

)

Separate +3.3V +0.3V/-0.165V isolated output buffer

supply (V

SNOOZE MODE for reduced power standby

Common data inputs and data outputs

Individual BYTE WRITE control and GLOBAL WRITE

Three chip enables for simple depth expansion and

address pipelining

Clock-controlled and registered addresses, data I/Os

and control signals

Internally self-timed WRITE cycle

Burst control pin (interleaved or linear burst)

Automatic power-down for portable applications

100-lead TQFP package for high density, high speed

Low capacitive bus loading

x18, x32 and x36 options available

MT58LC128K18C5, MT58LC64K32C5,

MT58LC64K36C5

3.3V Supply, Pipelined, Burst Counter and

Double-Cycle Deselect

100-Pin TQFP*

(SA-1)

*JEDEC-standard MS-026 BHA (LQFP).

OPTIONS

• Clock Cycle Timing

7.5ns/133 MHz

8.5ns/117 MHz

10ns/100 MHz

11ns/90 MHz

15ns/66 MHz

• Configurations

128K x 18

64K x 32

64K x 36

• Package

100-pin TQFP

MARKING

-7.5

-8.5

-10

-11

-15

MT58LC128K18C5

MT58LC64K32C5

MT58LC64K36C5

data inputs, active LOW chip enable (CE#), two additional

chip enables for easy depth expansion (CE2, CE2#), burst

control inputs (ADSC#, ADSP#, ADV#), byte write enables

(BWx#) and global write (GW#).

Asynchronous inputs include the output enable (OE#),

clock (CLK) and snooze enable (ZZ). There is also a burst

mode pin (MODE) that selects between interleaved and

linear burst modes. The data-out (Q), enabled by OE#, is

also asynchronous. WRITE cycles can be from one to two

bytes wide (x18) or from one to four bytes wide (x32/x36)

as controlled by the write control inputs.

Burst operation can be initiated with either address status

processor (ADSP#) or address status controller (ADSC#)

input pins. Subsequent burst addresses can be internally

generated as controlled by the burst advance pin (ADV#).

Address and write control are registered on-chip to

simplify WRITE cycles. This allows self-timed WRITE cycles.

Individual byte enables allow individual bytes to be written.

During WRITE cycles on the x18 device, BWa# controls

DQa pins and DQPa; BWb# controls DQb pins and DQPb.

During WRITE cycles on the x32 and x36 devices, BWa#

controls DQa pins and DQPa; BWb# controls DQb pins and

DQPb; BWc# controls DQc pins and DQPc; BWd# controls

DQd pins and DQPd. GW# LOW causes all bytes to be

• Part Number Example: MT58LC128K18C5LG-10

GENERAL DESCRIPTION

The Micron SyncBurst SRAM family employs high-

speed, low-power CMOS designs that are fabricated using

an advanced CMOS process.

The MT58LC128K18C5 and MT58LC64K32/36C5 SRAMs

integrate a 128K x 18, 64K x 32 or 64K x 36 SRAM core with

advanced synchronous peripheral circuitry and a 2-bit

burst counter. All synchronous inputs pass through registers

controlled by a positive-edge-triggered single clock input

(CLK). The synchronous inputs include all addresses, all

128K x 18, 64K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM

Y28.pm6 – Rev. 2/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Micron Technology, Inc.

PowerPC is a trademark of IBM Corporation.

Pentium is a registered trademark of Intel Corporation.

MT58LC128K18C5LG-11 Related Products

	MT58LC128K18C5LG-11	MT58LC128K18C5LG-15	MT58LC64K36C5LG-10	MT58LC64K36C5LG-11	MT58LC128K18C5LG-10	MT58LC64K32C5LG-15	MT58LC64K32C5LG-10
Description	Cache SRAM, 128KX18, 6ns, CMOS, PQFP100, MS-026, TQFP-100	Cache SRAM, 128KX18, 7ns, CMOS, PQFP100, MS-026, TQFP-100	Cache SRAM, 64KX36, 5ns, CMOS, PQFP100, MS-026, TQFP-100	Cache SRAM, 64KX36, 6ns, CMOS, PQFP100, MS-026, TQFP-100	Cache SRAM, 128KX18, 5ns, CMOS, PQFP100, MS-026, TQFP-100	Cache SRAM, 64KX32, 7ns, CMOS, PQFP100, MS-026, TQFP-100	Cache SRAM, 64KX32, 5ns, CMOS, PQFP100, MS-026, TQFP-100
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	Micron Technology	Micron Technology	Micron Technology	Micron Technology	Micron Technology	Micron Technology	Micron Technology
Parts packaging code	QFP	QFP	QFP	QFP	QFP	QFP	QFP
package instruction	MS-026, TQFP-100	MS-026, TQFP-100	MS-026, TQFP-100	MS-026, TQFP-100	MS-026, TQFP-100	MS-026, TQFP-100	MS-026, TQFP-100
Contacts	100	100	100	100	100	100	100
Reach Compliance Code	unknown	_compli	not_compliant	unknown	not_compliant	not_compliant	_compli
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	6 ns	7 ns	5 ns	6 ns	5 ns	7 ns	5 ns
Other features	BURST CONTROL; SELF TIMED WRITE CYCLE; REGISTER ADDRESS; BYTE WRITE CONTROL; AUTOMATIC POWER DOWN	BURST CONTROL; SELF TIMED WRITE CYCLE; REGISTER ADDRESS; BYTE WRITE CONTROL; AUTOMATIC POWER DOWN	BURST CONTROL; SELF TIMED WRITE CYCLE; REGISTER ADDRESS; BYTE WRITE CONTROL; AUTOMATIC POWER DOWN	BURST CONTROL; SELF TIMED WRITE CYCLE; REGISTER ADDRESS; BYTE WRITE CONTROL; AUTOMATIC POWER DOWN	BURST CONTROL; SELF TIMED WRITE CYCLE; REGISTER ADDRESS; BYTE WRITE CONTROL; AUTOMATIC POWER DOWN	BURST CONTROL; SELF TIMED WRITE CYCLE; REGISTER ADDRESS; BYTE WRITE CONTROL; AUTOMATIC POWER DOWN	BURST CONTROL; SELF TIMED WRITE CYCLE; REGISTER ADDRESS; BYTE WRITE CONTROL; AUTOMATIC POWER DOWN
Maximum clock frequency (fCLK)	90 MHz	66 MHz	100 MHz	90 MHz	100 MHz	66 MHz	100 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100
JESD-609 code	e0	e0	e0	e0	e0	e0	e0
length	20 mm	20 mm	20 mm	20 mm	20 mm	20 mm	20 mm
memory density	2359296 bit	2359296 bi	2359296 bit	2359296 bit	2359296 bit	2097152 bit	2097152 bi
Memory IC Type	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM
memory width	18	18	36	36	18	32	32
Number of functions	1	1	1	1	1	1	1
Number of terminals	100	100	100	100	100	100	100
word count	131072 words	131072 words	65536 words	65536 words	131072 words	65536 words	65536 words
character code	128000	128000	64000	64000	128000	64000	64000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	128KX18	128KX18	64KX36	64KX36	128KX18	64KX32	64KX32
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LQFP	LQFP	LQFP	LQFP	LQFP	LQFP	LQFP
Encapsulate equivalent code	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
power supply	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm
Maximum standby current	0.01 A	0.01 A	0.01 A	0.01 A	0.01 A	0.01 A	0.01 A
Minimum standby current	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V
Maximum slew rate	0.25 mA	0.2 mA	0.3 mA	0.25 mA	0.3 mA	0.2 mA	0.3 mA
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD
width	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm
Peak Reflow Temperature (Celsius)	235	-	235	235	235	235	235
Maximum time at peak reflow temperature	30	-	30	30	30	30	30

Recommended Resources

Homemade simple battery discharge meter circuit diagram

Wiring a when the leakage protector supplies power and lighting loads in the TN system

Voltage detection relay for battery pack charger

Using a "magic stick" to direct the circuit of a singing toy doll

Wireless long wave remote control composed of T630/T631

Remote control system composed of FDD400-1/JDD400-1

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components