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MT46V16M16TG-75Z:K

Description
16M X 16 DDR DRAM, 0.7 ns, PDSO66
Categorystorage   
File Size3MB,93 Pages
ManufacturerMicron
Websitehttp://www.micron.com/
Download Datasheet Parametric View All

MT46V16M16TG-75Z:K Overview

16M X 16 DDR DRAM, 0.7 ns, PDSO66

MT46V16M16TG-75Z:K Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals66
Maximum operating temperature70 Cel
Minimum operating temperature0.0 Cel
Maximum supply/operating voltage2.7 V
Minimum supply/operating voltage2.5 V
Rated supply voltage2.6 V
Minimum access time0.7000 ns
Processing package description0.40 INCH, lead FREE, plastic, TSOP-66
Lead-freeYes
EU RoHS regulationsYes
stateDISCONTINUED
CraftsmanshipCMOS
packaging shapeRectangle
Package SizeSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
surface mountYes
Terminal formGULL WING
Terminal spacing0.6500 mm
terminal coatingMATTE Tin
Terminal locationpair
Packaging MaterialsPlastic/Epoxy
Temperature levelCOMMERCIAL
memory width16
organize16M × 16
storage density2.68E8 deg
operating modeSynchronize
Number of digits1.68E7 words
Number of digits16M
Access methodFour BANK PAGE BURST
Memory IC typedouble rate synchronous dynamic random access memory dynamic random access memory
Number of ports1
256Mb: x4, x8, x16 DDR SDRAM
Features
Double Data Rate (DDR) SDRAM
MT46V64M4 – 16 Meg x 4 x 4 banks
MT46V32M8 – 8 Meg x 8 x 4 banks
MT46V16M16 – 4 Meg x 16 x 4 banks
Features
• V
DD
= +2.5V ±0.2V, V
DD
Q = +2.5V ±0.2V
• V
DD
= +2.6V ±0.1V, V
DD
Q = +2.6V ±0.1V (DDR400)
• Bidirectional data strobe (DQS) transmitted/
received with data, that is, source-synchronous data
capture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
(x16 has two – one per byte)
• Programmable burst lengths (BL): 2, 4, or 8
• Auto refresh
64ms, 8192-cycle(Commercial & Industrial)
16ms, 8192-cycle (Automotive)
• Self refresh (not available on AT devices)
• Longer-lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2-compatible)
• Concurrent auto precharge option supported
t
RAS lockout supported (
t
RAP =
t
RCD)
Options
Marking
• Configuration
64 Meg x 4 (16 Meg x 4 x 4 banks)
64M4
32 Meg x 8 (8 Meg x 8 x 4 banks)
32M8
16 Meg x 16 (4 Meg x 16 x 4 banks)
16M16
• Plastic package – OCPL
66-pin TSOP
TG
66-pin TSOP (Pb-free)
P
• Plastic package
FG
1
60-ball FBGA (8mm x 14mm)
BG
1
60-ball FBGA (8mm x 14mm) (Pb-free)
CV
2
60-ball FBGA (8mm x 12.5mm)
CY
2
60-ball FBGA (8mm x 12.5mm)
(Pb-free)
• Timing – cycle time
5ns @ CL = 3 (DDR400B)
-5B
6ns @ CL = 2.5 (DDR333) FBGA only
-6
6ns @ CL = 2.5 (DDR333) TSOP only
-6T
-75E
1
7.5ns @ CL = 2 (DDR266)
-75Z
1
7.5ns @ CL = 2 (DDR266A)
-75
1
7.5ns @ CL = 2.5 (DDR266B)
• Self refresh
Standard
None
Low-power self refresh
L
• Temperature rating
Commercial (0°C to +70°C)
None
Industrial (–40°C to +85°C)
IT
Automotive (–40°C to +105°C)
AT
4
• Revision
:G
3
x4, x8
:F
3
x16
x4, x8, x16
:K
Notes: 1. Only available on Revision F and G.
2. Only available on Revision K.
3. Not recommended for new designs.
4. Contact Micron for availability.
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
256Mb_DDR_x4x8x16_D1.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
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