CAT5419
Dual Digital
Potentiometer (POT)
with 64 Taps
and 2‐wire Interface
Description
http://onsemi.com
The CAT5419 is two digital POTs integrated with control logic and
16 bytes of NVRAM memory.
A separate 6-bit control register (WCR) independently controls the
wiper tap position for each digital POT. Associated with each wiper
control register are four 6-bit non-volatile memory data registers (DR)
used for storing up to four wiper settings. Writing to the wiper control
register or any of the non-volatile data registers is via a 2-wire serial
bus (I
2
C-like). On power-up, the contents of the first data register
(DR0) for each of the two potentiometers is automatically loaded into
its respective wiper control registers (WCR).
The Write Protection (WP) pin protects against inadvertent
programming of the data register.
The CAT5419 can be used as a potentiometer or as a two terminal,
variable resistor. It is intended for circuit level or system level
adjustments in a wide variety of applications.
Features
TSSOP24
Y SUFFIX
CASE 948AR
SOIC−24
W SUFFIX
CASE 751BK
PIN CONNECTIONS
V
CC
R
L0
R
H0
R
W0
A2
WP
SDA
A
1
R
L1
R
H1
R
W1
GND
SOIC−24 (W)
(Top View)
SDA
A
1
R
L1
R
H1
R
W1
GND
NC
NC
NC
NC
SCL
A
3
1
WP
A
2
R
W0
R
H0
R
L0
V
CC
NC
NC
NC
NC
A
0
NC
CAT5419
1
NC
NC
NC
NC
A
0
NC
A
3
SCL
NC
NC
NC
NC
Two Linear-taper Digital Potentiometers
64 Resistor Taps per Potentiometer
End to End Resistance 2.5 kW, 10 kW, 50 kW or 100 kW
Potentiometer Control and Memory Access via 2-wire Interface
(I
2
C like)
Low Wiper Resistance, Typically 80
W
Four Non-volatile Wiper Settings for Each Potentiometer
Recall of Wiper Settings at Power Up
2.5 to 6.0 Volt Operation
Standby Current less than 1
mA
1,000,000 Nonvolatile WRITE Cycles
100 Year Nonvolatile Memory Data Retention
24-lead SOIC and 24-lead TSSOP
Write Protection for Data Register
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
CAT5419
TSSOP24 (Y)
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
Semiconductor Components Industries, LLC, 2013
July, 2013
−
Rev. 11
1
Publication Order Number:
CAT5419/D
CAT5419
R
H0
R
H1
SCL
SDA
2−WIRE BUS
INTERFACE
WIPER
CONTROL
REGISTERS
R
W0
R
W1
WP
A0
A1
A2
A3
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
R
L0
R
L1
Figure 1. Functional Diagram
PIN DESCRIPTIONS
SCL: Serial Clock
The CAT5419 serial clock input pin is used to clock all
data transfers into or out of the device.
SDA: Serial Data
Table 1. PIN CONNECTIONS
Pin
SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Pin
TSSOP
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Name
V
CC
R
L0
R
H0
R
W0
A2
WP
SDA
A1
R
L1
R
H1
R
W1
GND
NC
NC
NC
NC
SCL
A3
NC
A0
NC
NC
NC
NC
Function
Supply Voltage
Low Reference Terminal
for Potentiometer 0
High Reference Terminal
for Potentiometer 0
Wiper Terminal for
Potentiometer 0
Device Address
Write Protection
Serial Data Input/Output
Device Address
Low Reference Terminal
for Potentiometer 1
High Reference Terminal
for Potentiometer 1
Wiper Terminal for
Potentiometer 1
Ground
No Connect
No Connect
No Connect
No Connect
Bus Serial Clock
Device Address
No Connect
Device Address, LSB
No Connect
No Connect
No Connect
No Connect
The CAT5419 bidirectional serial data pin is used to
transfer data into and out of the device. The SDA pin is an
open drain output and can be wire-OR’d with the other open
drain or open collector outputs.
A0, A1, A2, A3: Device Address Inputs
These inputs set the device address when addressing
multiple devices. A total of sixteen devices can be addressed
on a single bus. A match in the slave address must be made
with the address input in order to initiate communication
with the CAT5419.
R
H
, R
L
: Resistor End Points
The R
H
and R
L
pins are equivalent to the terminal
connections on a mechanical potentiometer.
The R
W
pins are equivalent to the wiper terminal of a
mechanical potentiometer.
WP: Write Protect Input
R
W
: Wiper
The WP pin when tied low prevents non-volatile writes to
the data registers (change of wiper control register is
allowed) and when tied high or left floating normal
read/write operations are allowed. See page 8, Write
Protection for more details.
http://onsemi.com
2
CAT5419
DEVICE OPERATION
The CAT5419 is two resistor arrays integrated with 2wire
serial interface logic, four 6-bit wiper control registers and
sixteen 6-bit, non-volatile memory data registers. Each
resistor array contains 63 separate resistive elements
connected in series. The physical ends of each array are
equivalent to the fixed terminals of a mechanical
potentiometer (R
H
and R
L
). R
H
and R
L
are symmetrical and
may be interchanged. The tap positions between and at the
ends of the series resistors are connected to the output wiper
terminals (R
W
) by a CMOS transistor switch. Only one tap
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Temperature Under Bias
Storage Temperature Range
Voltage to any Pins with Respect to V
SS
(Notes 1, 2)
V
CC
with Respect to GND
Package Power Dissipation Capability (T
A
= 25C)
Lead Soldering Temperature (10 s)
Wiper Current
Ratings
−55
to +125
−65
to +150
−2.0
to V
CC
+2.0
−2.0
to +7.0
1.0
300
12
Units
C
C
V
V
W
C
mA
point for each potentiometer is connected to its wiper
terminal at a time and is determined by the value of the wiper
control register. Data can be read or written to the wiper
control registers or the non-volatile memory data registers
via the 2-wire bus. Additional instructions allow data to be
transferred between the wiper control registers and each
respective potentiometer’s non-volatile data registers. Also,
the device can be instructed to operate in an
“increment/decrement” mode.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is
−0.5
V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+ 0.5 V, which may overshoot to V
CC
+ 2.0 V for periods of less than 20 ns.
2. Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1 V to V
CC
+ 1 V.
Table 3. RECOMMENDED OPERATING CONDITIONS
Parameters
V
CC
Industrial Temperature
Ratings
+2.5 to 6.0
−40
to +85
Units
V
C
http://onsemi.com
3
CAT5419
Table 4. POTENTIOMETER CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Symbol
R
POT
R
POT
R
POT
R
POT
Parameter
Potentiometer Resistance (−00)
Potentiometer Resistance (−50)
Potentiometer Resistance (−10)
Potentiometer Resistance (−25)
Potentiometer Resistance Tolerance
R
POT
Matching
Power Rating
I
W
R
W
R
W
V
TERM
V
N
Wiper Current
Wiper Resistance
Wiper Resistance
Voltage on any R
H
or R
L
Pin
Noise
Resolution
Absolute Linearity (Note 4)
Relative Linearity (Note 5)
TC
RPOT
TC
RATIO
C
H
/C
L
/C
W
fc
Temperature Coefficient of R
POT
Ratiometric Temp. Coefficient
Potentiometer Capacitances
Frequency Response
R
W(n)(actual)
−R
(n)(expected)
(Note 7)
R
W(n+1)
−[R
W(n)+LSB
]
(Note 7)
(Note 3)
(Note 3)
(Note 3)
R
POT
= 50 kW (Note 3)
10/10/25
0.4
300
20
I
W
=
3
mA @ V
CC
= 3 V
I
W
=
3
mA @ V
CC
= 5 V
V
SS
= 0 V
(Note 3)
GND
TBD
1.6
1
0.2
80
25C, each pot
Test Conditions
Min
Typ
100
50
10
2.5
20
1
50
6
300
150
V
CC
Max
Units
kW
kW
kW
kW
%
%
mW
mA
W
W
V
nV/Hz
%
LSB
(Note 6)
LSB
(Note 6)
ppm/C
ppm/C
pF
MHz
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
5. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer.
It is a measure of the error in step size.
6. LSB = R
TOT
/ 63 or (R
H
−
R
L
) / 63, single pot
7. n = 0, 1, 2, ..., 63
Table 5. D.C. OPERATING CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Symbol
I
CC
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL1
Parameter
Power Supply Current
Standby Current (V
CC
= 5 V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V
CC
= 3 V)
I
OL
= 3 mA
Test Conditions
f
SCL
= 400 kHz
V
IN
= GND or V
CC
; SDA Open
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
−1
V
CC
x 0.7
Min
Max
1
1
10
10
V
CC
x 0.3
V
CC
+ 1.0
0.4
Units
mA
mA
mA
mA
V
V
V
Table 6. PIN CAPACITANCE
(Note 8)
(Applicable over recommended operating range from T
A
= 25C, f = 1.0 MHz, V
CC
= +5.0 V (unless otherwise noted).)
Symbol
C
I/O
C
IN
Test Conditions
Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, A3, SCL, WP)
Min
Typ
Max
8
6
Units
pF
pF
Conditions
V
I/O
= 0 V
V
IN
= 0 V
http://onsemi.com
4
CAT5419
Table 7. A.C. CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Symbol
f
SCL
T
I
(Note 8)
t
AA
t
BUF
(Note 8)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
(Note 8)
t
F
(Note 8)
t
SU:STO
t
DH
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
Time the bus must be free before a new transmission can start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
0.6
50
1.2
0.6
1.2
0.6
0.6
0
100
0.3
300
Parameter
Min
Typ
Max
400
50
0.9
Units
kHz
ns
ms
ms
ms
ms
ms
ms
ns
ns
ms
ns
ms
ns
Table 8. POWER UP TIMING
(Note 8) (Over recommended operating conditions unless otherwise stated.)
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Min
Typ
Max
1
1
Units
ms
ms
8. This parameter is tested initially and after a design or process change that affects the parameter.
Table 9. WRITE CYCLES LIMITS
(Note 9)
Symbol
t
WR
Write Cycle Time
Parameter
Max
5
Units
ms
9. The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
Table 10. RELIABILITY CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Symbol
N
END
(Note 10)
T
DR
(Note 10)
V
ZAP
(Note 10)
I
LTH
(Notes 10, 11)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
Reference Test Method
MIL−STD−883, Test Method 1033
MIL−STD−883, Test Method 1008
MIL−STD−883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2,000
100
Typ
Max
Units
Cycles/Byte
Years
Volts
mA
10. This parameter is tested initially and after a design or process change that affects the parameter.
11. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
http://onsemi.com
5
京公网安备 11010802033920号
EEWORLD
