Integrated
Circuit
Systems, Inc.
ICS85211BI-03
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
F
EATURES
•
2 differential LVHSTL compatible outputs
•
1 differential CLK, nCLK input pair
•
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
Maximum output frequency: 700MHz
•
Translates any single-ended input signal to
LVHSTL levels with resistor bias on nCLK input
•
Output skew: 30ps (maximum)
•
Part-to-part skew: 250ps (maximum)
•
Propagation delay: 1.3ns (maximum)
•
Output duty cycle: 49% - 51% up to 266.6MHz
•
V
OH
= 1.15V (maximum)
•
3.3V operating supply
•
Lead-Free package available
•
-40°C to 85°C ambient operating temperature
G
ENERAL
D
ESCRIPTION
The ICS85211BI-03 is a low skew, high perfor-
mance 1-to-2 Differential-to-LVHSTL Fanout
HiPerClockS™
Buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions
from ICS. The CLK, nCLK pair can accept most
standard differential input levels.The ICS85211BI-03 is char-
acterized to operate from a 3.3V power supply. Guar-
anteed output and par t-to-par t skew characteristics
make the ICS85211BI-03 ideal for those clock distribu-
tion applications demanding well defined performance
and repeatability.
ICS
B
LOCK
D
IAGRAM
Q0
nQ0
Q1
nQ1
P
IN
A
SSIGNMENT
Q0
nQ0
Q1
nQ1
1
2
3
4
8
7
6
5
V
DD
CLK
nCLK
GND
CLK
nCLK
ICS85211BI-03
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
85211BMI-03
www.icst.com/products/hiperclocks.html
1
REV. B SEPTEMBER 14, 2004
Integrated
Circuit
Systems, Inc.
ICS85211BI-03
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
Type
Output
Output
Power
Input
Input
Power
Pullup/
Pulldown
Pullup
Description
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
Power supply ground.
Inver ting differential clock input. V
DD
/2 default when left floating.
Non-inver ting differential clock input.
Positive supply pin.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5
6
7
8
Name
Q0, nQ0
Q1, nQ1
GND
nCLK
CLK
V
DD
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
T
ABLE
3. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK
0
1
Biased; NOTE 1
Biased; NOTE 1
0
1
Q0, Q1
LOW
HIGH
LOW
HIGH
HIGH
LOW
Outputs
nQ0, nQ1
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
85211BMI-03
www.icst.com/products/hiperclocks.html
2
REV. B SEPTEMBER 14, 2004
Integrated
Circuit
Systems, Inc.
ICS85211BI-03
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
4.6V
-0.5V to V
DD
+ 0.5 V
50mA
100mA
112.7°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
55
Units
V
mA
T
ABLE
4B. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
nCLK
CLK
nCLK
CLK
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
150
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
0.5
V
CMR
NOTE 1, 2
NOTE 1: For single ended applications the maximum input voltage for CLK and nCLK is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
T
ABLE
4C. LVHSTL DC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, T
A
= -40°C
TO
85°C
Symbol Parameter
V
OH
V
OL
V
SWING
Output High Voltage
Output Low Voltage
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
0.7
0
0.3
0.65
Typical
Maximum
1.15
0.4
1.15
Units
V
V
V
85211BMI-03
www.icst.com/products/hiperclocks.html
3
REV. B SEPTEMBER 14, 2004
Integrated
Circuit
Systems, Inc.
ICS85211BI-03
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
Test Conditions
IJ 600MHz
Minimum
0.9
Typical
Maximum
700
1.3
30
250
20% to 80%
185
47
450
53
Units
MHz
ns
ps
ps
ps
%
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
t
sk(o)
t
sk(pp)
t
R
/ t
F
odc
IJ 266.6MHz
49
51
%
All parameters measured at 600MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
85211BMI-03
www.icst.com/products/hiperclocks.html
4
REV. B SEPTEMBER 14, 2004
Integrated
Circuit
Systems, Inc.
ICS85211BI-03
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V±5%
V
DD
Qx
SCOPE
V
DD
nCLK
LVHSTL
nQx
V
PP
Cross Points
V
CMR
CLK
GND
GND
0V
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
nQx
Qx
nQy
Qy
D
IFFERENTIAL
I
NPUT
L
EVEL
Qx
PART 1
nQx
Qy
PART 2
nQy
t
sk(o)
t
sk(pp)
O
UTPUT
S
KEW
P
ART
-
TO
-P
ART
S
KEW
nCLK
80%
80%
V
SW I N G
CLK
nQ0, nQ1
Q0, Q1
t
PD
Clock
Outputs
20%
t
R
t
F
20%
O
UTPUT
R
ISE
/F
ALL
T
IME
nQ0, nQ1
Q0, Q1
Pulse Width
t
PERIOD
P
ROPAGATION
D
ELAY
odc =
t
PW
t
PERIOD
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
P
ERIOD
85211BMI-03
www.icst.com/products/hiperclocks.html
5
REV. B SEPTEMBER 14, 2004
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