CAT9554, CAT9554A
8-bit I
2
C and SMBus I/O Port
with Interrupt
Description
The CAT9554 and CAT9554A are CMOS devices that provide 8−bit
parallel input/output port expansion for I
2
C and SMBus compatible
applications. These I/O expanders provide a simple solution in
applications where additional I/Os are needed: sensors, power
switches, LEDs, pushbuttons, and fans.
The CAT9554/9554A consist of an input port register, an output port
register, a configuration register, a polarity inversion register and an
I
2
C/SMBus−compatible serial interface.
Any of the eight I/Os can be configured as an input or output by
writing to the configuration register. The system master can invert the
CAT9554/9554A input data by writing to the active−high polarity
inversion register.
The CAT9554/9554A features an active low interrupt output which
indicates to the system master that an input state has changed.
The device’s extended addressing capability allows up to 8 devices
to share the same bus. The CAT9554A is identical to the CAT9554
except the fixed part of the I
2
C slave address is different. This allows
up to 16 of devices (eight CAT9554 and eight CAT9554A) to be
connected on the same bus.
Features
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SOIC−16
W SUFFIX
CASE 751BG
TQFN−16
HV4 SUFFIX
CASE 510AE
TSSOP−16
Y SUFFIX
CASE 948AN
PIN CONNECTIONS
A0
A1
A2
I/O
0
I/O
1
I/O
2
I/O
3
V
SS
1
V
CC
SDA
SCL
INT
I/O
7
I/O
6
I/O
5
I/O
4
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
400 kHz I
2
C Bus Compatible
(Note 1)
2.3 V to 5.5 V Operation
Low Stand−by Current
5 V Tolerant I/Os
8 I/O Pins that Default to Inputs at Power−up
High Drive Capability
Individual I/O Configuration
Polarity Inversion Register
Active Low Interrupt Output
Internal Power−on Reset
No Glitch on Power−up
Noise Filter on SDA/SCL Inputs
Cascadable up to 8 Devices
Industrial Temperature Range
16−lead SOIC and TSSOP, and 16−pad TQFN (4 x 4 mm) Packages
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
SOIC (W), TSSOP (Y)
(Top View)
A1
A0
V
CC
SDA
A2
I/O
0
I/O
1
I/O
2
1
SCL
INT
I/O
7
I/O
6
I/O
3
V
SS
I/O
4
I/O
5
TQFN 4 x 4 mm (HV4)
(Top View)
Applications
•
White Goods (dishwashers, washing machines)
•
Handheld Devices (cell phones, PDAs, digital cameras)
•
Data Communications (routers, hubs and servers)
1. All I/Os are set to inputs at RESET.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
©
Semiconductor Components Industries, LLC, 2011
June, 2011
−
Rev. 6
1
Publication Order Number:
CAT9554/D
CAT9554, CAT9554A
A0
A1
A2
SCL
SDA
INPUT
FILTER
I
2
C/SMBUS
CONTROL
8−BIT
WRITE pulse
READ pulse
V
CC
V
SS
POWER−ON
RESET
LP FILTER
INPUT/
OUTPUT
PORTS
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
INT
V
CC
Figure 1. Block Diagram
Table 1. PIN DESCRIPTION
SOIC / TSSOP
1
2
3
4−7
8
9−12
13
14
15
16
TQFN
15
16
1
2−5
6
7−10
11
12
13
14
Pin Name
A0
A1
A2
I/O
0−3
V
SS
I/O
4−7
INT
SCL
SDA
V
CC
Note: All I/Os are set to inputs at RESET.
Function
Address Input 0
Address Input 1
Address Input 2
Input/Output Port 0 to Input/Output Port 3
Ground
Input/Output Port 4 to Input/Output Port 7
Interrupt Output (open drain)
Serial Clock
Serial Data
Power Supply
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
V
CC
with Respect to Ground
Voltage on Any Pin with Respect to Ground
DC Current on I/O
0
to I/O
7
DC Input Current
V
CC
Supply Current
V
SS
Supply Current
Package Power Dissipation Capability (T
A
= 25°C)
Junction Temperature
Storage Temperature
Ratings
−0.5
to +6.5
−0.5
to +5.5
±50
±20
85
100
1.0
+150
−65
to +150
Units
V
V
mA
mA
mA
mA
W
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. RELIABILITY CHARACTERISTICS
Symbol
V
ZAP
(Note 2)
I
LTH
(Notes 2, 3)
Parameter
ESD Susceptibility
Latch−up
Reference Test Method
JEDEC Standard JESD 22
JEDEC Standard 17
Min
2000
100
Units
Volts
mA
2. This parameter is tested initially and after a design or process change that affects the parameter.
3. Latch−up protection is provided for stresses up to 100 mA on address and data pins from
−1
V to V
CC
+1 V.
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CAT9554, CAT9554A
Table 4. D.C. OPERATING CHARACTERISTICS
(V
CC
= 2.3 to 5.5 V; T
A
=
−40°C
to +85°C, unless otherwise specified.)
Symbol
SUPPLIES
V
CC
I
CC
I
stbl
I
stbh
V
POR
SCL, SDA, INT
V
IL
(Note 4)
V
IH
(Note 4)
I
OL
I
L
C
I
(Note 5)
C
O
(Note 5)
A0, A1, A2
V
IL
(Note 4)
V
IH
(Note 4)
I
LI
I/Os
V
IL
V
IH
I
OL
Low level input voltage
High level input voltage
Low level output current
V
OL
= 0.5 V; V
CC
= 2.3 V (Note 6)
V
OL
= 0.7 V; V
CC
= 2.3 V (Note 6)
V
OL
= 0.5 V; V
CC
= 4.5 V (Note 6)
V
OL
= 0.7 V; V
CC
= 4.5 V (Note 6)
V
OL
= 0.5 V; V
CC
= 3.0 V (Note 6)
V
OL
= 0.7 V; V
CC
= 3.0 V (Note 6)
V
OH
High level output
voltage
I
OH
=
−8
mA; V
CC
= 2.3 V (Note 7)
I
OH
=
−10
mA; V
CC
= 2.3 V (Note 7)
I
OH
=
−8
mA; V
CC
= 3.0 V (Note 7)
I
OH
=
−10
mA; V
CC
= 3.0 V (Note 7)
I
OH
=
−8
mA; V
CC
= 4.75 V (Note 7)
I
OH
=
−10
mA; V
CC
= 4.75 V (Note 7)
I
IH
I
IL
C
I
(Note 5)
C
O
(Note 5)
4.
5.
6.
7.
Input leakage current
Input leakage current
Input capacitance
Output capacitance
V
CC
= 3.6 V; V
I
= V
CC
V
CC
= 5.5 V; V
I
= V
SS
−0.5
2.0
8
10
8
10
8
10
1.8
1.7
2.6
2.5
4.1
4.0
−
−
−
−
−
−
10
13
17
24
14
19
−
−
−
−
−
−
−
−
−
−
0.8
5.5
−
−
−
−
−
−
−
−
−
−
−
−
1
−100
5
8
V
V
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
mA
mA
pF
pF
Low level input voltage
High level input voltage
Input leakage current
−0.5
2.0
−1
−
−
−
0.8
5.5
1
V
V
mA
Low level input voltage
High level input voltage
Low level output current
Leakage current
Input capacitance
Output capacitance
V
OL
= 0.4 V
V
I
= V
CC
or V
SS
V
I
= V
SS
V
O
= V
SS
−0.5
0.7 x V
CC
3
−1
−
−
−
−
−
−
−
−
0.3 x V
CC
5.5
−
+1
6
8
V
V
mA
mA
pF
pF
Supply voltage
Supply current
Standby current
Standby current
Power−on reset voltage
Operating mode; V
CC
= 5.5 V;
no load; f
SCL
= 100 kHz
Standby mode; V
CC
= 5.5 V; no load;
V
I
= V
SS
; f
SCL
= 0 kHz; I/O = inputs
Standby mode; V
CC
= 5.5 V; no load;
V
I
= V
CC
; f
SCL
= 0 kHz; I/O = inputs
No load; V
I
= V
CC
or V
SS
2.3
−
−
−
−
−
104
550
0.25
1.5
5.5
175
700
1
1.65
V
mA
mA
mA
V
Parameter
Conditions
Min
Typ
Max
Unit
V
IL min
and V
IH max
are reference values only and are not tested.
This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
The total current sunk by all I/Os must be limited to 100 mA and each I/O limited to 25 mA maximum.
The total current sourced by all I/Os must be limited to 85 mA.
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CAT9554, CAT9554A
Table 5. A.C. CHARACTERISTICS
(V
CC
= 2.3 V to 5.5 V; T
A
=
−40°C
to +85°C, unless otherwise specified.) (Note 8)
Standard I
2
C
Symbol
F
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
(Note 9)
t
F
(Note 9)
t
SU:STO
t
BUF
(Note 9)
t
AA
t
DH
T
i
(Note 9)
Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
Noise Pulse Filtered at SCL and SDA Inputs
100
100
4
4.7
3.5
50
100
4
4.7
4
4.7
0
250
1000
300
0.6
1.3
0.9
Parameter
Min
Max
100
0.6
1.3
0.6
0.6
0
100
300
300
Min
Fast I
2
C
Max
400
Units
kHz
ms
ms
ms
ms
ms
ns
ns
ns
ms
ms
ms
ns
ns
Symbol
PORT TIMING
t
PV
t
PS
t
PH
t
IV
t
IR
Output Data Valid
Input Data Setup Time
Input Data Hold Time
Parameter
Min
Max
Units
200
100
1
ns
ns
ms
INTERRUPT TIMING
Interrupt Valid
Interrupt Reset
4
4
ms
ms
8. Test conditions according to “AC Test Conditions” table.
9. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
Table 6. A.C. TEST CONDITIONS
Input Rise and Fall time
CMOS Input Voltages
CMOS Input Reference Voltages
TTL Input Voltages
TTL Input Reference Voltages
Output Reference Voltages
Output Load: SDA, INT
Output Load: I/Os
≤
10 ns
0.2 V
CC
to 0.8 V
CC
0.3 V
CC
to 0.7 V
CC
0.4 V to 2.4 V
0.8 V, 2.0 V
0.5 V
CC
Current Source I
OL
= 3 mA; C
L
= 100 pF
Current Source: I
OL
/I
OH
= 10 mA; C
L
= 50 pF
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CAT9554, CAT9554A
t
F
t
LOW
SCL
t
SU:STA
SDA IN
t
AA
SDA OUT
t
DH
t
BUF
t
HD:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
t
HIGH
t
R
t
LOW
Figure 2. I
2
C Serial Interface Timing
Pin Description
SCL: Serial Clock
A0, A1, A2: Device Address Inputs
The serial clock input clocks all data transferred into or out
of the device. The SCL line requires a pull−up resistor if it
is driven by an open drain output.
SDA: Serial Data/Address
These inputs are used for extended addressing capability.
The A0, A1, A2 pins should be hardwired to V
CC
or V
SS
.
When hardwired, up to eight CAT9554/9554As may be
addressed on a single bus system. The levels on these inputs
are compared with corresponding bits, A2, A1, A0, from the
slave address byte.
I/O
0
to I/O
7
: Input / Output Ports
The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire−ORed with other open drain or
open collector outputs. A pull−up resistor must be connected
from SDA line to V
CC
. The value of the pull−up resistor, R
P
,
can be calculated based on minimum and maximum values
from Figure 3 and Figure 4 (see Note).
Any of these pins may be configured as input or output.
The simplified schematic of I/O
0
to I/O
7
is shown in
Figure 5. When an I/O is configured as an input, the Q1 and
Q2 output transistors are off creating a high impedance input
with a weak pull−up resistor (typical 100 kW). If the I/O pin
is configured as an output, the push−pull output stage is
enabled. Care should be taken if an external voltage is
applied to an I/O pin configured as an output due to the low
impedance paths that exist between the pin and either V
CC
or V
SS
.
8
Fast Mode I
2
C Bus /
tr max
−
300 ns
2.5
I
OL
= 3 mA @ V
OLmax
2.0
1.5
1.0
0.5
0
R
Pmax
(KW)
R
Pmin
(KW)
7
6
5
4
3
2
1
2.0
2.4
2.8
3.2
3.6
4.0
4.4
4.8
5.2
5.6
0
0
50
100
150
200
250
300
350
400
V
CC
(V)
C
BUS
(pF)
Figure 3. Minimum R
P
Value vs.
Supply Voltage
NOTE:
Figure 4. Maximum R
P
Value vs.
Bus Capacitance
According to the Fast Mode I
2
C bus specification, for bus capacitance up to 200 pF, the pull up device can be a resistor. For bus
loads between 200 pF and 400 pF, the pull−up device can be a current source (Imax = 3 mA) or a switched resistor circuit.
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