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IMUI-67202AL-25

Description
FIFO, 1KX9, 25ns, Asynchronous, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28
Categorystorage    storage   
File Size181KB,17 Pages
ManufacturerTEMIC
Websitehttp://www.temic.de/
Download Datasheet Parametric View All

IMUI-67202AL-25 Overview

FIFO, 1KX9, 25ns, Asynchronous, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28

IMUI-67202AL-25 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerTEMIC
package instruction0.300 INCH, PLASTIC, SOJ-28
Reach Compliance Codeunknown
Maximum access time25 ns
Maximum clock frequency (fCLK)28.57 MHz
period time35 ns
JESD-30 codeR-PDSO-J28
JESD-609 codee0
memory density9216 bit
Memory IC TypeOTHER FIFO
memory width9
Number of functions1
Number of terminals28
word count1024 words
character code1000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize1KX9
Output characteristics3-STATE
ExportableNO
Package body materialPLASTIC/EPOXY
encapsulated codeSOJ
Encapsulate equivalent codeSOJ28,.34
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
power supply5 V
Certification statusNot Qualified
Maximum slew rate0.14 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationDUAL
M67201A/M67202A
512

9 & 1 K

9 CMOS Parallel FIFO
Introduction
The M67201A/202A implement a first-in first-out
algorithm, featuring asynchronous read/write operations.
The FULL and EMPTY flags prevent data overflow and
underflow. The Expansion logic allows unlimited
expansion in word size and depth with no timing
penalties. Twin address pointers automatically generate
internal read and write addresses, and no external address
information are required for the TEMIC FIFOs. Address
pointers are automatically incremented with the write pin
and read pin. The 9 bits wide data are used in data
communications applications where a parity bit for error
checking is necessary. The Retransmit pin reset the Read
pointer to zero without affecting the write pointer. This is
very useful for retransmitting data when an error is
detected in the system.
Using an array of eigh transistors (8 T) memory cell and
fabricated with the state of the art 1.0
µm
lithography
named SCMOS, the M 67201A/202A combine an
extremely low standby supply current (typ = 1.0
µA)
with
a fast access time at 25 ns over the full temperature range.
All versions offer battery backup data retention capability
with a typical power consumption at less than 5
µW.
For military/space applications that demand superior
levels
of
performance
and
reliability
the
M 67201A/202A is processed according to the methods
of the latest revision of the MIL STD 883 (class B or S)
and/or ESA SCC 9000.
Features
D
D
D
D
First-in first-out dual port memory
512
×
9 organisation (M 67201A)
1024
×
9 organisation (M 67202A)
Fast access time
20*, 25, 35, 45, 55 ns, commercial, industrial and
automotive
20*, 25, 30, 40, 50 ns, military
D
Wide temperature range :
– 55°C to + 125°C
D
67201AL/202AL low power 67201AV/202AV very low
power
D
Fully expandable by word width or depth
* Preview. Please Consult Sales.
D
D
D
D
D
D
D
D
Asynchronous read/write operations
Empty, full and half flags in single device mode
Retransmit capability
Bi-directional applications
Battery back-up operation : 2 V data retention
TTL compatible
Single 5 V
±
10 % Power Supply (1)
High performance SCMOS technology
(1) 3.3 V versions are also available. Please consult sales.
MATRA MHS
Rev. D (11 April. 97)
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