32Kx8 Bit High Speed Static RAM(3.3V Operating), Evolutionary Pin out.
CMOS SRAM
Revision History
Rev No.
Rev. 0.0
Rev. 1.0
History
Initial release with Preliminary.
Release to final Data Sheet.
1. Delete Preliminary
2.1. Add 28-TSOP1 Package.
3.1. Delete DIP Package.
3.2. Delete 20ns part
3.3. Add Capacitive load of the test environment in A.C test load
Draft Data
Jun. 1st, 1994
Oct. 4th, 1994
Remark
Preliminary
Final
Rev. 2.0
Rev. 3.0
Feb. 22th, 1996
Feb. 25th, 1998
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 3.0
February 1998
PRELIMINARY
KM68V257C
32K x 8 Bit High-Speed CMOS Static RAM (3.3V Operating)
FEATURES
• Fast Access Time 15, 17ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 30mA(Max.)
(CMOS) : 0.1mA(Max.)
Operating KM68V257C - 15 : 90mA(Max.)
KM68V257C - 17 : 80mA(Max.)
• Single 3.3±0.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• 2V Minimum Data Retention; L-ver. only
• Standard Pin Configuration
KM68V257CJ : 28-SOJ-300
KM68V257CTG : 28-TSOP1-0813, 4F
CMOS SRAM
GENERAL DESCRIPTION
The KM68V257C is a 262,144-bit high-speed Static Random
Access Memory organized as 32,768 words by 8 bits. The
KM68V257C uses 8 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG′s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The KM68V257C is packaged
in a 300mil 28-pin plastic SOJ or TSOP1 forward.
PIN CONFIGURATION
(Top View)
OE
A
11
A
9
A
8
A
13
WE
Vcc
A
14
A
12
A
7
A
6
A
5
A
4
A
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
10
CS
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
Vss
I/O
3
I/O
2
I/O
1
A
0
A
1
A
2
TSOP1
FUNCTIONAL BLOCK DIAGRAM
A
14
1
28 Vcc
27 WE
26 A
13
25 A
8
24 A
9
23 A
11
Clk Gen.
A
3
A
4
A
6
A
7
A
8
A
12
A
13
A
14
A
5
Pre-Charge-Circuit
A
12
2
A
7
3
A
6
4
Row Select
A
5
5
Memory Array
512 Rows
64x8 Columns
A
4
6
A
3
7
A
2
8
A
1
9
A
0
10
I/O
1
11
SOJ
22 OE
21 A
10
20 CS
19 I/O
8
18 I/O
7
17 I/O
6
16 I/O
5
15 I/O
4
I/O
1
~I/O
8
Data
Cont.
CLK
Gen.
A
0
I/O Circuit
Column Select
I/O
2
12
I/O
3
13
Vss 14
PIN FUNCTION
A
1
A
2
A
9
A
10
A
11
Pin Name
CS
WE
OE
A
0
- A
14
WE
CS
OE
I/O
1
~ I/O
8
V
CC
V
SS
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power(+3.3V)
Ground
-2-
Rev 3.0
February 1998
PRELIMINARY
KM68V257C
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Symbol
V
IN
, V
OUT
V
CC
P
D
T
STG
T
A
Rating
-0.5 to 4.6
-0.5 to 4.6
1.0
-65 to 150
0 to 70
Unit
V
V
W
°C
°C
CMOS SRAM
*
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(T
A
=0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
3.0
0
2.2
-0.3*
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+0.3**
0.8
Unit
V
V
V
V
*
V
IL
(Min) = -2.0(Pulse Width
≤
12ns) for I
≤
20mA
**
V
IH
(Max) = V
CC
+2.0V(Pulse Width
≤
12ns) for I
≤
20mA
DC AND OPERATING CHARACTERISTICS
(T
A
=0 to 70°C,V
CC
=3.3±0.3V, unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Operating Current
Symbol
I
LI
I
LO
I
CC
Test Conditions
V
IN
= V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
= V
SS
to V
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
= V
IH
or V
IL,
I
OUT
=0mA
Min. Cycle, CS=V
IH
f=0MHz, CS≥V
CC
-0.2V,
V
IN
≥V
CC
-0.2V or V
IN
≤0.2V
I
OL
=8mA
I
OH
=-4mA
15ns
17ns
Min
-2
-2
-
-
-
-
-
2.4
Max
2
2
90
80
30
0.1
0.4
-
mA
mA
V
V
Unit
µA
µA
mA
Standby Current
I
SB
I
SB1
Output Low Voltage Level
Output High Voltage Level
V
OL
V
OH
CAPACITANCE*
(T
A
=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
Symbol
C
I/O
C
IN
Test Conditions
V
I/O
=0V
V
IN
=0V
MIN
-
-
Max
8
7
Unit
pF
pF
* Capacitance is sampled and not 100% tested.
-3-
Rev 3.0
February 1998
PRELIMINARY
KM68V257C
AC CHARACTERISTICS
(T
A
=0 to 70°C, V
CC
=3.3±0.3V, unless otherwise noted.)
TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
Value
0V to 3V
3ns
1.5V
See below
CMOS SRAM
Output Loads(A)
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
+3.3V
R
L
= 50Ω
D
OUT
V
L
= 1.5V
Z
O
= 50Ω
30pF*
319Ω
D
OUT
353Ω
5pF*
* Capacitive Load consists of all components of the
京公网安备 11010802033920号
EEWORLD
