FIN1048 3.3V LVDS 4-Bit Flow-Through High Speed Differential Receiver
September 2001
Revised August 2003
FIN1048
3.3V LVDS 4-Bit Flow-Through
High Speed Differential Receiver
General Description
This quad receiver is designed for high speed interconnect
utilizing Low Voltage Differential Signaling (LVDS) technol-
ogy. The receiver translates LVDS levels, with a typical dif-
ferential input threshold of 100mV, to LVTTL signal levels.
LVDS provides low EMI at ultra low power dissipation even
at high frequencies. This device is ideal for high speed
transfer of clock and data.
The FIN1048 can be paired with its companion driver, the
FIN1047, or any other LVDS driver.
Features
s
Greater than 400Mbs data rate
s
Flow-through pinout simplifies PCB layout
s
3.3V power supply operation
s
0.4ns maximum differential pulse skew
s
2.5ns maximum propagation delay
s
Low power dissipation
s
Power-Off protection
s
Fail safe protection for open-circuit, shorted and termi-
nated conditions
s
Meets or exceeds the TIA/EIA-644 LVDS standard
s
Pin compatible with equivalent RS-422 and LVPECL
devices
s
16-Lead SOIC and TSSOP packages save space
Ordering Code:
Order Number
FIN1048M
FIN1048MTC
Package Number
M16A
MTC16
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Name
R
IN1+
, R
IN2+
, R
IN3+
, R
IN4+
R
IN1−
, R
IN2−
, R
IN3−
, R
IN4−
EN
EN
V
CC
GND
Description
Non-Inverting LVDS Inputs
Inverting LVDS Inputs
Driver Enable Pin
Inverting Driver Enable Pin
Power Supply
Ground
R
OUT1
, R
OUT2
, R
OUT3
, R
OUT4
LVTTL Data Outputs
Function Table
Inputs
EN
H
H
H
X
L or Open
H
=
HIGH Logic Level
Z
=
High Impedance
Outputs
R
IN+
H
L
X
X
R
OUT−
L
H
X
X
R
OUT
H
L
H
Z
Z
EN
L or Open
L or Open
H
X
L or Open Fail Safe Condition
L
=
LOW Logic Level
X
=
Don’t Care
Fail Safe
=
Open, Shorted, Terminated
© 2003 Fairchild Semiconductor Corporation
DS500588
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FIN1048
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Input Voltage (V
OUT
)
DC Output Current (I
O
)
Storage Temperature Range (T
STG
)
Max Junction Temperature (T
J
)
Lead Temperature (T
L
)
(Soldering, 10 seconds)
ESD (Human Body Model)
ESD (Machine Model)
260
°
C
−
0.5V to
+
4.6V
−
0.5V to
+
4.6V
−
0.5V to 6V
16 mA
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Magnitude of Differential Voltage
(|V
ID
|)
Common-Mode Input Voltage (V
IC
)
Input Voltage (V
IN
)
Operating Temperature (T
A
)
100mV to V
CC
0.05V to 2.35V
0 to V
CC
3.0V to 3.6V
−
65
°
C to
+
150
°
C
150
°
C
−
40
°
C to
+
85
°
C
≥
10,000V
≥
450V
Note 1:
The “Absolute Maximum Ratings”: are those values beyond which
damage to the device may occur. The databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperature and output/input loading variables. Fairchild
does not recommend operation of circuits outside databook specification.
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
V
TH
V
TL
I
IN
I
I(OFF)
V
IH
V
IL
V
OH
V
OL
I
OZ
V
IK
I
CCZ
I
CC
C
IN
C
OUT
Parameter
Differential Input Threshold HIGH
Differential Input Threshold LOW
Input Current
Power-Off Input Current
Input High Voltage (EN or EN)
Input Low Voltage (EN or EN)
Output HIGH Voltage
Output LOW Voltage
Disabled Output Leakage Current
Input Clamp Voltage
Disabled Power Supply Current
Power Supply Current
Input Capacitance
Output Capacitance
I
OH
= −100 µA
I
OH
= −8
mA
I
OH
=
100
µA
I
OL
=
8 mA
EN
=
0.8 and EN*
=
2V, V
OUT
=
3.6V or 0V
I
IK
= −18
mA
Receiver Disabled
Receiver Enabled, (R
IN
+
=
1V and R
IN
−
=
1.4V)
or (R
IN
+
=
1.4V and R
IN
−
=
1V)
3.5
6
−1.5
5
15
Test Conditions
See Figure 1 and Table 1
See Figure 1 and Table 1
V
IN
=
0V or V
CC
V
CC
=
0V, V
IN
=
0V or 3.6V
2.0
GND
V
CC
−0.2
2.4
0.2
0.5
±20
−100
±20
±20
V
CC
+
1.0
0.8
Min
Typ
(Note 2)
100
Max
Units
mV
mV
µA
µA
V
V
V
V
µA
V
mA
mA
pF
pF
Note 2:
All typical values are at T
A
=
25°C and with V
CC
=
3.3V.
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FIN1048
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
t
PLH
t
PHL
t
TLH
t
THL
t
SK(P)
t
SK(LH)
t
SK(HL)
t
SK(PP)
f
MAX
t
ZH
t
ZL
t
HZ
t
LZ
Parameter
Propagation Delay LOW-to-HIGH
Propagation Delay HIGH-to-LOW
Output Rise Time (20% to 80%)
Output Fall Time (80% to 20%)
Pulse Skew |t
PLH
- t
PHL
|
Channel-to-Channel Skew
(Note 4)
Part-to-Part Skew (Note 5)
Maximum Operating Frequency
(Note 6)
LVTTL Output Enable Time from Z to HIGH
LVTTL Output Enable Time from Z to LOW
LVTTL Output Disable Time from HIGH to Z
LVTTL Output Disable Time from LOW to Z
R
L
=
1kΩ, C
L
=
10 pF,
See Figure 3
R
L
=
1kΩ, C
L
=
10 pF,
see Figure 1 and Figure 2
200
375
6.0
6.0
6.0
6.0
|V
ID
|
=
400 mV, C
L
=
10 pF,
R
L
=
1kΩ
See Figure 1 and Figure 2
Test Conditions
Min
1.0
1.0
0.7
0.7
Typ
(Note 3)
2.5
2.5
1.2
1.2
0.4
0.3
1.0
Max
Units
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
Note 3:
All typical values are at T
A
=
25°C and with V
CC
=
3.3V.
Note 4:
t
SK(LH)
, t
SK(HL)
is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc-
tion.
Note 5:
t
SK(PP)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6:
f
MAX
Criteria: Input t
R
= t
F
<
1 ns, V
ID
=
300 mV, (1.05V to 1.35V pp), 50% duty cycle; Output duty cycle 40% to 60%, V
OL
<
0.5V, V
OH
>
2.4V.
All channels switching in phase.
Note A:
All differential input pulses have frequency
=
10MHz, t
R
or t
F
=
1ns
Note B:
C
L
includes all probe and jig capacitances
FIGURE 1. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit
TABLE 1. Receiver Minimum and Maximum Input Threshold Test Voltages
Applied Voltages (V)
V
IA
1.25
1.15
2.4
2.3
0.1
0
1.5
0.9
2.4
1.8
0.6
0
V
IB
1.15
1.25
2.3
2.4
0
0.1
0.9
1.5
1.8
2.4
0
0.6
Resulting Differential Input
Voltage (mA)
V
ID
100
−100
100
−100
100
−100
600
−600
600
−600
600
−600
Resulting Common Mode Input
Voltage (V)
V
IC
1.2
1.2
2.35
2.35
0.05
0.05
1.2
1.2
2.1
2.1
0.3
0.3
3
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FIN1048
FIGURE 2. LVDS Input to LVTTL Output AC Waveforms
Test Circuit for LVTTL Outputs
Voltage Waveforms Enable and Disable Times
FIGURE 3. LVTTL Outputs Test Circuit and AC Waveforms
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FIN1048
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
5
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