A42MX16-FVQ100IX39 datasheet, PDF

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A42MX16-FVQ100IX39: DescriptionField Programmable Gate Array, 1232-Cell, CMOS, PQFP100,; CategoryProgrammable logic devices Programmable logic; File Size3MB，115 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

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A42MX16-FVQ100IX39 Overview

Field Programmable Gate Array, 1232-Cell, CMOS, PQFP100,

A42MX16-FVQ100IX39 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Microsemi
package instruction	QFP, TQFP100,.63SQ
Reach Compliance Code	unknown
JESD-30 code	S-PQFP-G100
Number of entries	140
Number of logical units	1232
Output times	140
Number of terminals	100
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	TQFP100,.63SQ
Package shape	SQUARE
Package form	FLATPACK
power supply	3.3,3.3/5,5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD

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5.1

40MX and 42MX FPGA Families

Fe a t ur es

High C apaci t y

•

Single-Chip ASIC Alternative

3,000 to 54,000 System Gates

Up to 2.5 kbits Configurable Dual-Port SRAM

Fast Wide-Decode Circuitry

Up to 202 User-Programmable I/O Pins

5.6 ns Clock-to-Out

250 MHz Performance

5 ns Dual-Port SRAM Access

100 MHz FIFOs

7.5 ns 35-Bit Address Decode

• Commercial, Military Temperature and MIL-STD-883

Ceramic Packages

• QML Certification

• Ceramic Devices Available to DSCC SMD

E ase of Int egr at io n

• Mixed Voltage Operation (5.0V or 3.3V I/O)

• Synthesis-Friendly Architecture to Support ASIC Design

Methodologies

• Up to 100% Resource Utilization and 100% Pin Fixing

• Deterministic, User-Controllable Timing

• Unique In-System Diagnostic and Verification Capability

with Silicon Explorer II

• Low Power Consumption

• IEEE Standard 1149.1 (JTAG) Boundary Scan Testing

• 5.0V and 3.3V Programmable PCI-Compliant I/O

High P er f or m ance

HiR el Feat ur es

• Commercial, Industrial, and Military Temperature Plastic

Packages

Pr od uc t P r o f i l e

Device

Capacity

A40MX02

A40MX04

A42MX09

A42MX16

A42MX24

A42MX36

System Gates

SRAM Bits

Logic Modules

3,000

N/A

—

295

—

9.5 ns

N/A

—

147

44, 68

100

—

6,000

N/A

—

547

—

9.5 ns

N/A

—

273

44, 68, 84

100

—

14,000

N/A

348

336

N/A

5.6 ns

N/A

348

516

104

100, 160

100

176

—

24,000

N/A

624

608

N/A

6.1 ns

N/A

624

928

140

100, 160, 208

100

176

—

36,000

N/A

954

912

6.1 ns

N/A

954

1,410

176

Yes

160, 208

—

176

—

54,000

2,560

1,230

1,184

6.3 ns

1,230

1,822

202

Yes

—

208, 240

—

208, 256

272

Sequential

Combinatorial

Decode

Clock-to-Out

SRAM Modules

(64x4 or 32x8)

Dedicated Flip-Flops

Maximum Flip-Flops

Clocks

User I/O

(Maximum)

PCI

Boundary Scan Test (BST)

Packages

(by pin count)

PLCC

PQFP

VQFP

TQFP

CQFP

PBGA

O c t o be r 2 0 0 3

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