530AA289M000BG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 530AA289M000BG

530AA289M000BG: DescriptionLVPECL Output Clock Oscillator, 289MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size268KB，15 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530AA289M000BG Overview

LVPECL Output Clock Oscillator, 289MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530AA289M000BG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	50%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	289 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.0 7/06

Si530/531

Recommended Resources

Field output circuit: TA8445K circuit diagram

Fully automatic charger circuit that can automatically identify polarity

Typical energy-saving lamp ballast circuit diagram composed of IR51H420

DC servo motor control system circuit diagram

Pressure sensor remote interface circuit

555 "Happy Birthday to You" Electronic Candle Circuit

Hey, I can't write infrared decoding for msp430, and I don't know where the problem is. Can anyone give me some advice? Thank you.: 1 The infrared decoding subroutine is as follows: a[4] stores the user code, user inverse code and key data code, key data inverse code in sequence 2 Use the falling edge of P1.7 to trigger an interru...; 江汉大学南瓜 Microcontroller MCU

Various ground wires: (1) Digital ground: also called logic ground, is the zero potential of various switching (digital) signals. (2) Analog ground: is the zero potential of various analog signals. (3) Signal ground: usual...; eeleader FPGA/CPLD

Sending a KEYUP event: When a key is pushed up, a command is sent to execute the KEYUP event. How can I write it? It doesn't take much time....; axiulam1977 Embedded System

Wireless Control of Smart Light Bulbs (IoTT Caravan) --EEWORLD University: Wireless Control of Smart Light Bulbs (IoTT Caravan) : https://training.eeworld.com.cn/course/2212...; chenyy DIY/Open Source Hardware

Reflection and Reconstruction (More): [i=s]This post was last edited by Xin Xin on 2016-10-2 02:05[/i] Originally I just wanted to post these contents in the log in the space. After all, this is not a specific problem or code. Moreover, r...; 辛昕 Programming Basics

The difference between civilian-grade, industrial-grade and military-grade chips: I used to work in a military enterprise. From the incoming materials of various electronic components to the testing of various electronic components to the first piece testing, it is really a chain o...; alan000345 TI Technology Forum

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components