01
DS2413
1-Wire Dual Channel
Addressable Switch
www.maxim-ic.com
GENERAL DESCRIPTION
The DS2413 is a dual-channel programmable I/O 1-
Wire
®
chip. The PIO outputs are configured as open-
drain and provide up to 20mA continuous sink
capability and off-state operating voltage up to 28V.
Control and sensing of the PIO pins is performed with
a dedicated device-level command protocol. To
provide a high level of fault tolerance in the end
application, the 1-Wire IO and PIO pins are all
capable of withstanding continuous application of
voltages up to 28V max. Communication and
operation of the DS2413 is performed with the single
contact Maxim/Dallas 1-Wire serial interface.
FEATURES
Open-Drain Programmable I/O Pins
PIO Pins Support 20mA max Continuous Current
Sink
Supports 28V (max) PIO Pin Operating Voltage
On-Resistance of PIO Pulldown Transistor 20Ω
max; OFF Resistance 1MΩ min
Parasitic Power Supply Through 1-Wire
Communicates to Host with a Single Digital
Signal at 14.9kb or 100kbps Using 1-Wire
Protocol
Unique 64-bit ROM Serial Number Factory
Lasered Into Each Device
Switchpoint Hysteresis and Filtering to Optimize
Performance in the Presence of Noise
1-Wire IO Pin Supports 28V Absolute Maximum
DC Level for Fault Conditions
Operates Over a Wide 1-Wire Voltage Range of
2.8V to 5.25V from 0°C to +70°C
High ESD Immunity of 1-Wire IO Pin: 8kV HBM
Typical
TSOC package
APPLICATIONS
LED Control
Accessory Identification and Control
General Purpose Input/Output
Key-Pick Systems
Industrial Controllers
System Monitoring
TYPICAL OPERATING CIRCUIT
V
CC
R
PUP
DS2413
PIOA
PX.Y
IO
R2
PIOB
LED
R1
ORDERING INFORMATION
PART
DS2413P+
DS2413P+T&R
TEMP RANGE
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
TSOC
TSOC Tape-and-
Reel
µC
GND
Switch
Local
Power
+ Denotes a lead-free package.
Contact factory for availability of the TDFN package
PIN CONFIGURATION
TSOC
DS
2413
ywwrr
Commands, Registers, and Modes are capitalized for
clarity.
1-Wire is a registered trademark of Dallas Semiconductor Corp.
TDFN
6
5
4
1
2
3
6
5
4
1
2
3
Exposed Paddle
Top View with Marking. TDFN Contacts
Not Visible in this View.
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
2413
ymrrF
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REV: 112007
DS2413: 1-Wire Dual Channel Addressable Switch
ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin to GND
Maximum Current into IO Pin
Maximum Current into PIO Pin
Maximum Current Through GND Pins (Both Pins Tied Together)
Operating Temperature Range
Junction Temperature
Storage Temperature Range
Soldering Temperature
-0.5V, +30V
±
25mA
±
30mA
±
60mA
0°C to +70°C
+150°C
-55°C to +125°C
See IPC/JEDEC J-STD-020A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
PARAMETER
IO PIN GENERAL DATA
SYMBOL
CONDITIONS
MIN
TYP
T
A
= 0°C to +70°C
MAX
UNITS
1-Wire Pullup Voltage
(Note 1)
1-Wire Pullup Resistance
Input Load Current
Input Capacitance
Input Low Voltage
High-to-Low Switching
Threshold
Low-to-High Switching
Threshold
Switching Hysteresis
Output Low Voltage
V
PUP
R
PUP
I
L
C
IO
V
IL
V
TL
V
TH
V
HY
V
OL
Standard speed
Overdrive speed
DC only; no 1-Wire communication
(Notes 1, 2)
V
PUP
≤
5.25V
V
PUP
≤
3.30V
V(IO) = 28V (Note 3)
At 25°C (Notes 4, 5)
(Notes 1, 6)
(Notes 5, 7, 8)
(Notes 5, 7, 9)
2.8
2.9
1.5
3.5
3.5
400
5.25
5.25
28
2.2
70
15
950
800
0.4
3.2
3.6
0.4
V
k
Ω
µA
pF
V
V
V
V
V
µs
0.4
0.7
0.2
5
2
5
0.5
Not applicable (0)
65
67
9
10
480
600
48
63
15
15
2
2
0.24
0.24
0
0
60
60
8
8
(Notes 5, 10)
At 4mA Current Load (Note 11)
Standard speed, R
PUP
= 2.2k
Ω
Recovery Time
Overdrive speed, R
PUP
= 2.2k
Ω
t
REC
(Notes 1, 12)
Overdrive speed, directly prior to reset
pulse; R
PUP
= 2.2k
Ω
Rising-Edge Hold-off Time
Standard speed
t
REH
(Notes 5, 13)
Overdrive speed
Standard speed, V
PUP
≥
4.5V
Standard speed (Note 14)
Time slot Duration
t
SLOT
Overdrive speed, V
PUP
≥
4.5V
(Note 1, 5)
(Note 14)
Overdrive speed (Note 14)
IO PIN, 1-Wire RESET, PRESENCE DETECT CYCLE
Standard speed, V
PUP
≥
4.5V
Standard speed (Note 14)
Reset Low Time (Note 1)
t
RSTL
Overdrive speed, V
PUP
≥
4.5V
Overdrive speed (Note 14)
Standard speed, V
PUP
≥
4.5V
Presence Detect High
Standard speed
t
PDH
Time (Notes 14, 15)
Overdrive speed, V
PUP
≥
4.5V
Overdrive speed
Standard speed, V
PUP
> 4.5V
Standard speed
Presence Detect Fall Time
t
FPD
(Notes 5, 16)
Overdrive speed, V
PUP
≥
4.5V
Overdrive speed
Standard speed, V
PUP
> 4.5V
Standard speed (Note 14)
Presence Detect Low
t
PDL
Overdrive speed, V
PUP
≥
4.5V
Time (Note 15)
(Note 14)
Overdrive speed (Note 14)
5.0
µs
µs
960
960
80
80
66
68
7.0
8.2
1.4
1.6
0.7
0.9
240
260
25
32
µs
µs
µs
µs
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DS2413: 1-Wire Dual Channel Addressable Switch
PARAMETER
SYMBOL
CONDITIONS
Standard speed, V
PUP
> 4.5V
Standard speed
Overdrive speed, V
PUP
≥
4.5V
Overdrive speed
MIN
67.4
69.6
7.7
9.1
TYP
MAX
75
75
10
10
UNITS
Presence Detect Sample
Time (Notes 1, 20)
IO PIN, 1-Wire WRITE
t
MSP
µs
Write-0 Low Time
(Notes 1, 17)
Write-1 Low Time
(Notes 1, 17)
IO PIN, 1-Wire READ
Read Low Time
(Notes 1, 18)
Read Sample Time
(Notes 1, 18)
PIO Pins
Leakage Current
Input Capacitance
Output low voltage
Input Low Voltage
Input High Voltage
(Note 21)
Note 1:
Note 2:
t
W0L
t
W1L
Standard speed, V
PUP
> 4.5V
Standard speed (Note 14)
Overdrive speed, V
PUP
≥
4.5V
(Note 14)
Overdrive speed (Note 14)
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Pin at 28V (Note 19)
(Note 5)
20mA load current
(Note 1)
(Note 1)
60
62
7
8
5
1
5
1
t
RL
+
δ
t
RL
+
δ
8.5
100
120
120
16
16
15
2
15 -
δ
2-
δ
15
2
24
0.4
0.8
µs
µs
t
RL
t
MSR
I
LP
C
P
V
OLP
V
ILP
V
IHP
µs
µs
µA
pF
V
V
V
V
PUP
–
0.3V
28
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Note 17:
Note 18:
Note 19:
Note 20:
Note 21:
System requirement.
Full R
PUP
range guaranteed by design and simulation. not production tested. Production testing performed at a fixed R
PUP
value.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The
specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily
loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required.
The I-V characteristic is linear for voltages greater than 10V.
Capacitance on the data pin could be 800pF when V
PUP
is first applied. If a 2.2kΩ resistor is used to pull up the data line, 2.5µs
after V
PUP
has been applied the parasite capacitance will not affect normal communications.
Guaranteed by design and simulation. Not production tested.
The voltage on IO needs to be less than or equal to V
ILMAX
whenever the master drives the line low.
V
TL
and V
TH
are functions of the internal supply voltage, which is a function of V
PUP
and the 1-Wire Recovery Times. The V
TH
and
V
TL
maximum specifications are valid at V
PUPmax
(5.25V). In any case, V
TL
< V
TH
< V
PUP
.
Voltage below which, during a falling edge on IO, a logic 0 is detected.
Voltage above which, during a rising edge on IO, a logic 1 is detected.
After V
TH
is crossed during a rising edge on IO, the voltage on IO has to drop by at least V
HY
to be detected as logic '0'.
The I-V characteristic is linear for voltages less than 1V.
Applies to a single DS2413 attached to a 1-Wire line.
The earliest recognition of a negative edge is possible at t
REH
after V
TH
has been previously reached.
Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table below.
t
PDH
is deemed to have ended when the voltage on IO drops below 80% of V
PUP
on the leading edge of the presence-detect low
pulse. t
PDL
is deemed to have begun when the voltage on IO drops below 20% of V
PUP
on the leading edge of the pulse.
Interval during the negative edge on IO at the beginning of a Presence Detect pulse between the time at which the voltage is
80% of V
PUP
and the time at which the voltage is 20% of V
PUP
.
ε
in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to V
TH
. The actual maximum
duration for the master to pull the line low is t
W1Lmax
+ t
F
-
ε
and t
W0Lmax
+ t
F
-
ε
respectively.
δ
in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to the input high threshold
of the bus master. The actual maximum duration for the master to pull the line low is t
RLmax
+ t
F
.
The I-V characteristic is linear for voltages greater than 7V.
t
MSP
is a system required sample point and not directly production tested. Production testing is performed on related parameters
t
PDH
and t
PDL
. Parameter t
FPD
is guaranteed by design and simulation, not production tested.
Production tested for V
IHP(min)
. V
IHP(max)
is guaranteed by design and simulation, not production tested.
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DS2413: 1-Wire Dual Channel Addressable Switch
LEGACY VALUES
STANDARD SPEED
OVERDRIVE SPEED
MIN
MAX
MIN
MAX
61µs
(undef.)
7µs
(undef.)
480µs
(undef.)
48µs
80µs
15µs
60µs
2µs
6µs
60µs
240µs
8µs
24µs
60µs
120µs
6µs
16µs
DS2413 VALUES
STANDARD SPEED
OVERDRIVE SPEED
MIN
MAX
MIN
MAX
67µs
(undef.)
10µs
(undef.)
600µs
960µs
63µs
80µs
15µs
68µs
2µs
8.2µs
60µs
260µs
8µs
32µs
62µs
120µs
8µs
16µs
PARAMETER
t
SLOT
(incl. t
REC
)
t
RSTL
t
PDH
t
PDL
t
W0L
PIN DESCRIPTION
NAME
IO
PIOA
PIOB
GND1
GND2
NC
GND
TSOC PIN #
2
6
4
1
5
3
N/A
TDFN PIN #
2
4
6
3
5
1
EP
FUNCTION
1-Wire bus interface. Open-drain, requires external pullup resistor.
Programmable I/O pin, open-drain with weak pulldown, power-on
default is off (PIOA = 1).
Programmable I/O pin, open-drain with weak pulldown, power-on
default is off (PIOB = 1).
Ground reference 1
Ground reference 2; both GND pins must be connected in the
application.
Not connected
Exposed Paddle. Solder evenly to the board’s ground plane for proper
operation. See
Application Note 3273
for additional information.
DESCRIPTION
The DS2413 combines two PIO pins and a fully featured 1-Wire interface in a single chip. PIO outputs are open-
drain, operate at up to 28V and provide an on resistance of 20Ω max. A robust communication protocol ensures
that PIO output changes occur error-free. Each DS2413 has a Registration Number that is 64 bits long. The
Registration Number guarantees unique identification and is used to address the device in a multidrop 1-Wire
network environment, where multiple devices reside on a common 1-Wire bus and operate independently of each
other. Device power is supplied parasitically from the 1-Wire bus. The DS2413’s applications of include accessory
identification and control, system monitoring, and general-purpose input/output.
OVERVIEW
The block diagram in Figure 1 shows the relationships between the major sections of the DS2413. The DS2413
has two main components: 64-bit Registration Number, and PIO Control. The hierarchical structure of the 1-Wire
protocol is shown in Figure 2. The bus master must first provide one of the seven ROM Function Commands, 1)
Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5) Resume, 6) Overdrive-Skip ROM or 7) Overdrive-
Match ROM. Upon completion of an Overdrive ROM command byte executed at standard speed, the device enters
Overdrive mode where all subsequent communication occurs at a higher speed. The protocol required for these
ROM function commands is described in Figure 10. After a ROM function command is successfully executed, the
PIO functions become accessible and the master may provide one of the two PIO Function commands. The
protocol for these commands is described in Figure 6.
All data is read and written least significant bit first.
Figure 1. Block Diagram
Internal V
DD
PIOB
PIOA
IO
1-Wire
Interface
PIO
Control
64-Bit Registration
Number
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DS2413: 1-Wire Dual Channel Addressable Switch
64-BIT LASERED ROM
Each DS2413 has a unique ROM Registration Number that is 64 bits long, as shown in Figure 3. The first eight bits
are a 1-Wire family code. The next 48 bits are a unique serial number. The last eight bits are a CRC (Cyclic
Redundancy Check) of the first 56 bits. The 1-Wire CRC is generated using a polynomial generator consisting of a
shift register and XOR gates as shown in Figure 4. The polynomial is X
8
+ X
5
+ X
4
+ 1. Additional information about
the Dallas 1-Wire CRC is available in
Application Note 27.
The shift register bits are initialized to zero. Then
starting with the LSB of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been
entered, then the serial number is entered. After the 48th bit of the serial number has been entered, the shift
register contains the CRC value. Shifting in the eight bits of CRC should return the shift register to all zeros.
Figure 2. Hierarchical Structure for 1-Wire Protocol
DS2413
Command
Level:
Available
Commands:
Read ROM
Match ROM
Search ROM
Skip ROM
Resume
Overdrive Skip
Overdrive Match
Command
Codes:
33h
55h
F0h
CCh
A5h
3Ch
69h
Data Field
Affected:
64-bit Reg. #, RC-Flag
64-bit Reg. #, RC-Flag
64-bit Reg. #, RC-Flag
RC-Flag
RC-Flag
RC-Flag, OD-Flag
64-bit Reg. #, RC-Flag,
OD-Flag
1-Wire ROM Function
Commands (see Figure 10)
DS2413-specific
PIO Function Commands
(see Figure 6)
PIO Access Read
PIO Access Write
F5h
5Ah
PIO Pins
PIO Pins
Figure 3. 64-Bit LASERED ROM
MSB
8-Bit CRC Code
MSB
LSB
MSB
48-Bit Serial Number
LSB
LSB
8-Bit Family Code (3Ah)
MSB
LSB
Figure 4. 1-Wire CRC Generator
Polynomial = X + X + X + 1
8
5
4
1
STAGE
st
2
STAGE
nd
3
STAGE
rd
4
STAGE
th
5
STAGE
th
6
STAGE
th
7
STAGE
th
8
STAGE
th
X
0
X
1
X
2
X
3
X
4
X
5
X
6
X
7
X
8
INPUT DATA
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