GS867238AGE-450T datasheet, PDF

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GS867238AGE-450T: DescriptionStandard SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165; Categorystorage storage; File Size813KB，30 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

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GS867238AGE-450T Overview

Standard SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

GS867238AGE-450T Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	GSI Technology
Parts packaging code	BGA
package instruction	LBGA,
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
JESD-609 code	e1
length	17 mm
memory density	75497472 bit
Memory IC Type	STANDARD SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2MX36
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15 mm

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GS8672D20/38AE-550/500/450/400

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• 2.5 Clock Latency

• On-Chip ECC with virtually zero SER

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard package

• Dual Double Data Rate interface

• Byte Write Capability

• Burst of 4 Read and Write

• On-Die Termination (ODT) on Data (D), Byte Write (BW),

and Clock (K, K) outputs

• 1.8 V +100/–100 mV core power supply

• 1.5 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with 144Mb and future 288Mb devices

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

72Mb SigmaQuad

-II+

Burst of 4 ECCRAM

Clocking and Addressing Schemes

550 MHz–400 MHz

1.8 V V

1.5 V I/O

The GS8672D20/38AE SigmaQuad-II+ ECCRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Because Separate I/O SigmaQuad-II+ B4 RAMs always

transfer data in four packets, A0 and A1 are internally set to 0

for the first read or write transfer, and automatically

incremented by 1 for the next transfers. Because the LSBs are

tied off internally, the address field of a SigmaQuad-II+ B4

RAM is always two address pins less than the advertised index

depth (e.g., the 4M x 18 has a 1M addressable index).

On-Chip Error Correction Code

GSI's ECCRAMs implement an ECC algorithm that detects

and corrects all single-bit memory errors, including those

induced by Soft Error Rate (SER) events such as cosmic rays,

alpha particles. The resulting SER of these devices is

anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude

improvement over comparable SRAMs with no On-Chip ECC,

which typically have an SER of 200 FITs/Mb or more. SER

quoted above is based on reading taken at sea level.

However, the On-Chip Error Correction (ECC) will be

disabled if a “Half Write” operation is initiated. See the

Byte

Write Contol

section for further information.

SigmaQuad™ ECCRAM Overview

The GS8672D20/38AE are built in compliance with the

SigmaQuad-II+ ECCRAM pinout standard for Separate I/O

synchronous ECCRAMs. They are 75,497,472-bit (72Mb)

ECCRAMs. The GS8672D20/38AE SigmaQuad ECCRAMs

are just one element in a family of low power, low voltage

HSTL I/O ECCRAMs designed to operate at the speeds needed

to implement economical high performance networking

systems.

Parameter Synopsis

-550

tKHKH

tKHQV

1.81 ns

0.45ns

-500

2.0 ns

0.45 ns

-450

2.2 ns

0.45ns

-400

2.5 ns

0.45 ns

Rev: 1.00 5/2010

1/30

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8672D20/38AE-550/500/450/400

Background

Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are

needed. Therefore, the SigmaQuad-II+ ECCRAM interface and truth table are optimized for alternating reads and writes. Separate

I/O SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers

from Separate I/O ECCRAMs can cut the RAM’s bandwidth in half.

Alternating Read-Write Operations

SigmaQuad-II+ ECCRAMs follow a few simple rules of operation.

- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.

- Read or Write data transfers in progress may not be interrupted.

- R and W high always deselects the RAM.

- All address, data, and control inputs are sampled on clock edges.

In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for

details.

SigmaQuad-II+ B4 ECCRAM DDR Read

The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on

the Read Enable pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. Clocking

in a high on the Read Enable pin, R, begins a read port deselect cycle.

SigmaQuad-II+ B4 ECCRAM DDR Write

The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on

the Write Enable pin, W, and a high on the Read Enable pin, R, begins a write cycle. W is always ignored if the previous command

was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge of K, and

finally by the next rising edge of K.

Rev: 1.00 5/2010

5/30

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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