GS832218E-225M datasheet, PDF - EEWORLD Datasheet

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GS832218E-225M: DescriptionCache SRAM, 2MX18, 7ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, FPBGA-165; Categorystorage storage; File Size679KB，39 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

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GS832218E-225M Overview

Cache SRAM, 2MX18, 7ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, FPBGA-165

GS832218E-225M Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	GSI Technology
Parts packaging code	BGA
package instruction	LBGA, BGA165,11X15,40
Contacts	165
Reach Compliance Code	unknown
ECCN code	3A991.B.2.B
Maximum access time	7 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE, IT ALSO OPERATES AT AS 3.3V SUPPLY
Maximum clock frequency (fCLK)	225 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B165
length	17 mm
memory density	37748736 bit
Memory IC Type	CACHE SRAM
memory width	18
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	2MX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
power supply	2.5/3.3 V
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum standby current	0.2 A
Minimum standby current	2.3 V
Maximum slew rate	0.28 mA
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	15 mm

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GS832218/36(B/E)-225M

GS832272C-225M

119-, 165-, & 209-Pin BGA

Military Temp

Features

• Military Temperature Range

• FT pin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• ZQ mode pin for user-selectable high/low output drive

• 2.5 V +10%/–10% core power supply

• 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119-, 165-, and 209-bump BGA package

• RoHS-compliant packages available

2M x 18, 1M x 36, 512K x 72

36Mb S/DCD Sync Burst SRAMs

225 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

either linear or interleave order with the Linear Burst Order (LBO)

input. The Burst function need not be used. New addresses can be

loaded on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the

user via the FT mode . Holding the FT mode pin low places the

RAM in Flow Through mode, causing output data to bypass the

Data Output Register. Holding FT high places the RAM in

Pipeline mode, activating the rising-edge-triggered Data Output

SCD and DCD Pipelined Reads

The GS832218/36/72-225M is a SCD (Single Cycle Deselect) and

DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD

SRAMs pipeline disable commands to the same degree as read

commands. SCD SRAMs pipeline deselect commands one stage

less than read commands. SCD RAMs begin turning off their

outputs immediately after the deselect command has been

captured in the input registers. DCD RAMs hold the deselect

command for one full cycle and then begin turning off their

outputs just after the second rising edge of clock. The user may

configure this SRAM for either mode of operation using the SCD

mode input.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write control

inputs.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ low)

for multi-drop bus applications and normal drive strength (ZQ

floating or high) point-to-point applications. See the Output Driver

Characteristics chart for details.

Functional Description

Applications

The GS832218/36/72-225M is a

37,748,736

-bit high

performance synchronous SRAM with a 2-bit burst address

counter. Although of a type originally developed for Level 2

Cache applications supporting high performance CPUs, the device

now finds application in synchronous SRAM applications, ranging

from DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

ADV. The burst address counter may be configured to count in

Parameter Synopsis

-225M

(x18/x36)

(x72)

tCycle

Curr (x18)

Curr (x36)

Curr (x72)

tCycle

Curr (x18)

Curr (x36)

Curr (x72)

2.7

3.0

4.4

315

415

460

7.0

230

325

360

Unit

Pipeline

3-1-1-1

Flow Through

2-1-1-1

Rev: 1.00 1/2011

1/39

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS832218E-225M Related Products

	GS832218E-225M	GS832272C-225MT	GS832272C-225M	GS832236E-225M	GS832236E-225MT	GS832236B-225M	GS832236B-225MT	GS832218E-225MT	GS832218B-225MT	GS832218B-225M
Description	Cache SRAM, 2MX18, 7ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, FPBGA-165	Cache SRAM, 512KX72, 7ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209	Cache SRAM, 512KX72, 7ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209	Cache SRAM, 1MX36, 7ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, FPBGA-165	Cache SRAM, 1MX36, 7ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, FPBGA-165	Cache SRAM, 1MX36, 7ns, CMOS, PBGA119, 22 X 14 MM, 1.27 MM PITCH, FPBGA-119	Cache SRAM, 1MX36, 7ns, CMOS, PBGA119, 22 X 14 MM, 1.27 MM PITCH, FPBGA-119	Cache SRAM, 2MX18, 7ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, FPBGA-165	Cache SRAM, 2MX18, 7ns, CMOS, PBGA119, 22 X 14 MM, 1.27 MM PITCH, FPBGA-119	Cache SRAM, 2MX18, 7ns, CMOS, PBGA119, 22 X 14 MM, 1.27 MM PITCH, FPBGA-119
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	LBGA, BGA165,11X15,40	LBGA, BGA209,11X19,40	LBGA, BGA209,11X19,40	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40	BGA, BGA119,7X17,50	BGA, BGA119,7X17,50	LBGA, BGA165,11X15,40	BGA, BGA119,7X17,50	BGA, BGA119,7X17,50
Contacts	165	209	209	165	165	119	119	165	119	119
Reach Compliance Code	unknown	compliant	compliant	unknown	unknown	unknown	unknown	unknown	unknown	unknown
ECCN code	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B
Maximum access time	7 ns	7 ns	7 ns	7 ns	7 ns	7 ns	7 ns	7 ns	7 ns	7 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE, IT ALSO OPERATES AT AS 3.3V SUPPLY	FLOW-THROUGH OR PIPELINED ARCHITECTURE, IT ALSO OPERATES AT AS 3.3V SUPPLY	FLOW-THROUGH OR PIPELINED ARCHITECTURE, IT ALSO OPERATES AT AS 3.3V SUPPLY	FLOW-THROUGH OR PIPELINED ARCHITECTURE, IT ALSO OPERATES AT AS 3.3V SUPPLY	FLOW-THROUGH OR PIPELINED ARCHITECTURE, IT ALSO OPERATES AT AS 3.3V SUPPLY	FLOW-THROUGH OR PIPELINED ARCHITECTURE, IT ALSO OPERATES AT AS 3.3V SUPPLY	FLOW-THROUGH OR PIPELINED ARCHITECTURE, IT ALSO OPERATES AT AS 3.3V SUPPLY	FLOW-THROUGH OR PIPELINED ARCHITECTURE, IT ALSO OPERATES AT AS 3.3V SUPPLY	FLOW-THROUGH OR PIPELINED ARCHITECTURE, IT ALSO OPERATES AT AS 3.3V SUPPLY	FLOW-THROUGH OR PIPELINED ARCHITECTURE, IT ALSO OPERATES AT AS 3.3V SUPPLY
Maximum clock frequency (fCLK)	225 MHz	225 MHz	225 MHz	225 MHz	225 MHz	225 MHz	225 MHz	225 MHz	225 MHz	225 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-PBGA-B165	R-PBGA-B209	R-PBGA-B209	R-PBGA-B165	R-PBGA-B165	R-PBGA-B119	R-PBGA-B119	R-PBGA-B165	R-PBGA-B119	R-PBGA-B119
length	17 mm	22 mm	22 mm	17 mm	17 mm	22 mm	22 mm	17 mm	22 mm	22 mm
memory density	37748736 bit	37748736 bit	37748736 bit	37748736 bit	37748736 bit	37748736 bit	37748736 bit	37748736 bit	37748736 bit	37748736 bit
Memory IC Type	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM
memory width	18	72	72	36	36	36	36	18	18	18
Number of functions	1	1	1	1	1	1	1	1	1	1
Number of terminals	165	209	209	165	165	119	119	165	119	119
word count	2097152 words	524288 words	524288 words	1048576 words	1048576 words	1048576 words	1048576 words	2097152 words	2097152 words	2097152 words
character code	2000000	512000	512000	1000000	1000000	1000000	1000000	2000000	2000000	2000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
organize	2MX18	512KX72	512KX72	1MX36	1MX36	1MX36	1MX36	2MX18	2MX18	2MX18
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LBGA	LBGA	LBGA	LBGA	LBGA	BGA	BGA	LBGA	BGA	BGA
Encapsulate equivalent code	BGA165,11X15,40	BGA209,11X19,40	BGA209,11X19,40	BGA165,11X15,40	BGA165,11X15,40	BGA119,7X17,50	BGA119,7X17,50	BGA165,11X15,40	BGA119,7X17,50	BGA119,7X17,50
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY	GRID ARRAY	GRID ARRAY, LOW PROFILE	GRID ARRAY	GRID ARRAY
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
power supply	2.5/3.3 V	2.5/3.3 V	2.5/3.3 V	2.5/3.3 V	2.5/3.3 V	2.5/3.3 V	2.5/3.3 V	2.5/3.3 V	2.5/3.3 V	2.5/3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.5 mm	1.7 mm	1.7 mm	1.5 mm	1.5 mm	1.99 mm	1.99 mm	1.5 mm	1.99 mm	1.99 mm
Maximum standby current	0.2 A	0.2 A	0.2 A	0.2 A	0.2 A	0.2 A	0.2 A	0.2 A	0.2 A	0.2 A
Minimum standby current	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V
Maximum slew rate	0.28 mA	0.39 mA	0.39 mA	0.36 mA	0.36 mA	0.36 mA	0.36 mA	0.28 mA	0.28 mA	0.28 mA
Maximum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
Minimum supply voltage (Vsup)	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	1 mm	1 mm	1.27 mm	1.27 mm	1 mm	1.27 mm	1.27 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	15 mm	14 mm	14 mm	15 mm	15 mm	14 mm	14 mm	15 mm	14 mm	14 mm
Maker	GSI Technology	GSI Technology	GSI Technology	GSI Technology	GSI Technology	-	-	GSI Technology	GSI Technology	GSI Technology
Base Number Matches	-	1	1	1	1	1	1	-	-	-

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