MC74VHCT86A
Quad 2-Input XOR Gate /
CMOS Logic Level Shifter
with LSTTL−Compatible Inputs
The MC74VHCT86A is an advanced high speed CMOS 2−input
Exclusive−OR gate fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and
the output has a full 5 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logic−level translator from
3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic
to 3.0 V CMOS Logic while operating at the high−voltage power
supply.
The MC74VHCT86A input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows it to be used to interface 5 V circuits to 3 V circuits. The output
structures also provide protection when V
CC
= 0 V. These input and
output structures help prevent device destruction caused by supply
voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
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14−LEAD SOIC
D SUFFIX
CASE 751A
14−LEAD TSSOP
DT SUFFIX
CASE 948G
PIN CONNECTION AND
MARKING DIAGRAM
(Top View)
V
CC
14
B4
13
A4
12
Y4
11
B3
10
A3
9
Y3
8
•
•
•
•
•
•
•
•
•
•
•
High Speed: t
PD
= 4.8 ns (Typ) at V
CC
= 5 V
Low Power Dissipation: I
CC
= 2
mA
(Max) at T
A
= 25°C
TTL−Compatible Inputs: V
IL
= 0.8 V; V
IH
= 2.0 V
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Designed for 2 V to 5.5 V Operating Range
Low Noise: V
OLP
= 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: HBM > 2000 V; Machine Model > 200 V
These Devices are Pb−Free and are RoHS Compliant
1
A1
2
B1
3
Y1
4
A2
5
B2
6
Y2
7
GND
For detailed package marking information, see the Marking
Diagram section on page 4 of this data sheet.
FUNCTION TABLE
Inputs
A
L
L
H
H
B
L
H
L
H
Output
Y
L
H
H
L
LOGIC DIAGRAM
A1
B1
A2
B2
A3
B3
A4
B4
1
3
2
4
6
5
9
8
10
12
11
13
Y4
Y2
Y = A)B
Y3
Y1
ORDERING INFORMATION
Device
MC74VHCT86ADR2G
Package
Shipping
SOIC−14 2500 / Tape &
(Pb−Free)
Reel
MC74VHCT86ADTR2G TSSOP−14 2500 / Tape &
Reel
(Pb−Free)
©
Semiconductor Components Industries, LLC, 2014
1
November, 2014 − Rev. 3
Publication Order Number:
MC74VHCT86A/D
MC74VHCT86A
MAXIMUM RATINGS
Symbol
V
CC
V
in
V
out
I
IK
I
OK
I
out
I
CC
P
D
T
stg
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current (V
OUT
< GND; V
OUT
> V
CC
)
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air,
Storage Temperature
SOIC Package†
TSSOP Package†
V
CC
= 0
High or Low State
Parameter
Value
– 0.5 to + 7.0
– 0.5 to + 7.0
– 0.5 to + 7.0
– 0.5 to V
CC
+ 0.5
− 20
±
20
±
25
±
50
500
450
– 65 to + 150
Unit
V
V
V
mA
mA
mA
mA
mW
_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Characteristics
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V
CC
= 0
High or Low State
V
CC
= 3.3V
±
0.3V
V
CC
= 5.0V
±
0.5V
Symbol
V
CC
V
IN
V
OUT
T
A
t
r
, t
f
Min
2.0
0.0
0.0
0.0
−55
0
0
Max
5.5
5.5
5.5
V
CC
+85
100
20
Unit
V
V
V
°C
ns/V
Operating Temperature Range
Input Rise and Fall Time
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
NOISE CHARACTERISTICS
(Input t
r
= t
f
= 3.0ns, C
L
= 50pF, V
CC
= 5.0V, Measured in SOIC Package)
T
A
= 25°C
Symbol
V
OLP
V
OLV
V
IHD
V
ILD
Characteristic
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
Typ
0.3
− 0.3
Max
0.8
− 0.8
3.5
1.5
Unit
V
V
V
V
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2
MC74VHCT86A
DC ELECTRICAL CHARACTERISTICS
V
CC
Symbol
V
IH
Parameter
Minimum High−Level
Input Voltage
Maximum Low−Level
Input Voltage
Minimum High−Level
Output Voltage
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OH
= −50μA
V
IN
= V
IH
or V
IL
I
OH
= −4mA
I
OH
= −8mA
V
IN
= V
IH
or V
IL
I
OL
= 50μA
V
IN
= V
IH
or V
IL
I
OL
= 4mA
I
OL
= 8mA
V
IN
= 5.5V or GND
V
IN
= V
CC
or GND
Input: V
IN
= 3.4V
V
OUT
= 5.5V
Test Conditions
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
3.0
4.5
3.0
4.5
3.0
4.5
0 to
5.5
5.5
5.5
0.0
2.9
4.4
2.58
3.94
0.0
0.0
0.1
0.1
0.36
0.36
±0.1
2.0
1.35
0.5
3.0
4.5
Min
1.2
2.0
2.0
0.53
0.8
0.8
2.9
4.4
2.48
3.80
0.1
0.1
0.44
0.44
±1.0
20
1.50
5.0
T
A
= 25°C
Typ
Max
T
A
≤
85°C
Min
1.2
2.0
2.0
0.53
0.8
0.8
2.9
4.4
2.34
3.66
0.1
0.1
0.52
0.52
±1.0
40
1.65
10
μA
μA
mA
μA
V
V
Max
T
A
≤
125°C
Min
1.2
2.0
2.0
0.53
0.8
0.8
Max
Unit
V
V
IL
V
V
OH
V
V
V
OL
Maximum Low−Level
Output Voltage
V
IN
= V
IH
or V
IL
I
IN
I
CC
I
CCT
I
OPD
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
Quiescent Supply
Current
Output Leakage
Current
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
AC ELECTRICAL CHARACTERISTICS
(Input t
r
= t
f
= 3.0ns)
T
A
= 25°C
Symbol
t
PLH
,
t
PHL
Parameter
Propagation Delay,
A or B to Y
Test Conditions
V
CC
= 3.3
±
0.3V
V
CC
= 5.0
±
0.5V
C
in
Input Capacitance
C
L
= 15pF
C
L
= 50pF
C
L
= 15pF
C
L
= 50pF
Min
Typ
7.0
9.5
4.8
6.3
4
Max
11.0
14.5
6.8
8.8
10
T
A
= − 40 to 85°C
Min
1.0
1.0
1.0
1.0
Max
13.0
16.5
8.0
10.0
10
pF
Unit
ns
Typical @ 25°C, V
CC
= 5.0V
18
C
PD
Power Dissipation Capacitance (Note 1)
pF
1. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
/ 4 (per gate). C
PD
is used to determine the
no−load dynamic power consumption; P
D
= C
PD
V
CC2
f
in
+ I
CC
V
CC
.
TEST POINT
A or B
50%
GND
t
PLH
Y
t
PHL
V
OH
50% V
CC
V
OL
*Includes all probe and jig capacitance
3.0V
OUTPUT
DEVICE
UNDER
TEST
C
L
*
Figure 1. Switching Waveforms
Figure 2. Test Circuit
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3
MC74VHCT86A
MARKING DIAGRAMS
(Top View)
14
13
12
11
10
9
8
14 13 12 11 10
VHCT
86A
ALYWG
G
5
6
7
1
2
3
4
5
6
7
9
8
VHCT86AG
AWLYWW*
1
2
3
4
14−LEAD SOIC
D SUFFIX
CASE 751A
14
13
12
11
10
9
8
14−LEAD TSSOP
DT SUFFIX
CASE 948G
74VHCT86A
ALYWG*
1
2
3
4
5
6
7
14−LEAD SOEIAJ
M SUFFIX
CASE 965
A
WL, L
Y
WW, W
G or
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*See Applications Note #AND8004/D for date code and traceability information.
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4
MC74VHCT86A
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G
ISSUE B
14X
K
REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
_
8
_
INCHES
MIN MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.020 0.024
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0
_
8
_
0.10 (0.004)
0.15 (0.006) T U
S
M
T U
S
V
S
N
2X
L/2
14
8
0.25 (0.010)
M
L
PIN 1
IDENT.
1
7
B
−U−
N
F
DETAIL E
K
K1
J J1
0.15 (0.006) T U
S
A
−V−
SECTION N−N
−W−
C
0.10 (0.004)
−T−
SEATING
PLANE
D
G
H
DETAIL E
SOLDERING FOOTPRINT
7.06
1
14X
0.36
14X
1.26
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5
ÉÉÉ
ÇÇÇ
ÉÉÉ
ÇÇÇ
0.65
PITCH
DIMENSIONS: MILLIMETERS
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