EEWORLDEEWORLDEEWORLD

Part Number

Search

LJT06RP-25-24SB

Description
MIL Series Connector, 24 Contact(s), Aluminum Alloy, Female, Crimp Terminal, Plug
CategoryThe connector    The connector   
File Size209KB,1 Pages
ManufacturerAmphenol
Websitehttp://www.amphenol.com/
Download Datasheet Parametric View All

LJT06RP-25-24SB Overview

MIL Series Connector, 24 Contact(s), Aluminum Alloy, Female, Crimp Terminal, Plug

LJT06RP-25-24SB Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerAmphenol
Reach Compliance Codecompliant
Other featuresSTANDARD: MIL-DTL-38999, COMPATIBLE CONTACTS: 10-597261-161; 10-597261-121
Back shell typeSOLID
Body/casing typePLUG
Connector typeMIL SERIES CONNECTOR
Contact to complete cooperationNOT SPECIFIED
Contact point genderFEMALE
Contact materialNOT SPECIFIED
Coupling typeBAYONET
DIN complianceNO
empty shellNO
Filter functionNO
IEC complianceNO
MIL complianceYES
Manufacturer's serial numberLJT06RP
Mixed contactsNO
Installation typeCABLE
OptionsGENERAL PURPOSE
Shell surfaceCADMIUM PLATED
Shell materialALUMINUM ALLOY
Housing size25
Termination typeCRIMP
Total number of contacts24
LJT06R (MS27467)
— crimp
straight plug
* LJT06RE-XX-XXX (MS27467E)
* LJT06RT-XX-XXX (MS27467T)
* LJT06RP-XX-XXX (MS27467P)
* To complete order number see page 49.
V Thread
Class 2A
(Plated)
KK
Dia.
Max.
Shell
Size
F
Dia.
L
Max.
Q
Max.
9
11
13
15
17
19
21
23
25
.327
.444
.558
.683
.808
.909
1.034
1.159
1.284
1.531
1.531
1.531
1.531
1.531
1.531
1.625
1.625
1.625
.844
.969
1.141
1.266
1.391
1.500
1.625
1.750
1.875
.4375-28 UNEF
.5625-24 UNEF
.6875-24 UNEF
.8125-20 UNEF
.9375-20 UNEF
1.0625-18 UNEF
1.1875-18 UNEF
1.3125-18 UNEF
1.4375-18 UNEF
.608
.734
.858
.984
1.110
1.234
1.360
1.484
1.610
All dimensions for reference only.
33
【Signal Processing】: Classic material "FPGA Implementation of Digital Signal Processing" Chinese and English versions, etc.
最近恰好在研究数字信号处理的FPGA实现问题,搜集了几本实用的书籍: 《数字信号处理的FPGA实现》及其所附带光盘的vhdl、verilog代码,挺有用的 大家可以看看,还有无线通信FPGA设计 田耕等编著的《无线通信FPGA设计 》及其matlab和verilog代码XILINX指定的培训教材:《无线通信的MATLAB和FPGA实现》[西瑞克斯] Attached: All Verilog so...
mlk123 FPGA/CPLD
STM32 Network SMI Interface
1Introduction to Ethernet The Ethernet peripheral of STM32F20X and STM32F21 can receive and send data according to the IEEE802.3-2002 standard.Ethernet provides a complete and flexible peripheral to m...
嵌入式enjoy stm32/stm8
A method to avoid latches in Verilog
To avoid latches, you can pre-assign unconditional default values to variables in an ALWAYS block, as follows: This is a relatively simple way to avoid latches. I personally think that even if the def...
eeleader FPGA/CPLD
Cyclone3 I/O logic level compatibility issue
I use FPGA's 3, 4, 5, 6 banks to connect to DDR1 interface. DDR's I/O voltage is 2.5V, but I connected the VCCIO of these banks of FPGA to 3.3V. What impact will this have on the subsequent circuit de...
happysheep224 FPGA/CPLD
CC3200-LAUNCHXL Development Board
The development board has complete documentation and is easy to use. I used IAR7.2.0 + cc3200sdk-1.3.0-windows-installer.exe + CC3x00ServicePack-1.0.1.13-2.11.0.1-windows-installer.exe to build the pl...
Jacktang Wireless Connectivity

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1326  2362  457  1925  2256  27  48  10  39  46 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号