NB4L7210
2.5V/3.3V Differential 2x10
Crosspoint Clock Driver
with SDI Programmable
Output Selects
The NB4L7210 is a Clock input crosspoint fanout distribution
device selecting between one of two input clocks on each of the 10
differential output pairs. A 10 Bit Serial Data Interface programs each
output MUX to asynchronously select either Input clock.
CLOCK inputs can accept LVCMOS, LVTTL, LVPECL, CML, or
LVDS signal levels and incorporate an internal 50 ohms on die
termination resistors. SCLK, SDATA, and SLOAD input can accept
single ended LVPECL, CML, LVCMOS, LVTTL signals levels.
SCLK and SDATA inputs operate up to 20 MHz. SLOAD input
loads and latches the output select data. The SDATAOUT pin permits
cascading multiple devices. Outputs are optimized for minimal
output−to−output skew and low jitter.
Features
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MARKING
DIAGRAM*
52
1
1
52
QFN52
MN SUFFIX
CASE 485M
NB4L7210
A
WL
YY
WW
G
NB4L
7210
AWLYYWWG
•
•
•
•
•
•
•
•
•
•
•
Typical Input Clock Frequency > 2 GHz
200 ps Typical Rise and Fall Times
800 ps Typical Propagation Delay
Output to Output Skew 150 ps
Additive RMS Phase Jitter of 0.2 ps
Operating Range: V
CC
= 2.375 V to 3.6 V with V
EE
= 0 V
Differential LVPECL Output Level (Typ 700 mV Peak−to−Peak)
Low Profile 8x8 mm, 52 QFN Package
10GE WAN: 155.52 MHz / 622.08 MHz
10GE LAN: 161.1328 MHz
These are Pb−Free Devices*
= Device Code
= Assembly Site
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
Q0
Q0b
VTCLK0
CLK0
CLK0b
VTCLK0b
Q1
Q1b
VTCLK1
CLK1
CLK1b
VTCLK1b
Q8
Q8b
Q9
Q9b
VCC
VEE
SCLK
SDATA
SLOAD
SDATAOUT
Figure 1. Functional Block Diagram
ORDERING INFORMATION
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
©
Semiconductor Components Industries, LLC, 2015
1
March, 2015 − Rev. 8
Publication Order Number:
NB4L7210/D
NB4L7210
SDATAOUT
VCC0
VCC1
VCC2
GND
VCC
Q0
Q0
Q1
Q1
GND
Q2
Q2
Exposed Pad (EP)
52 51 50 49 48 47 46 45 44 43 42 41 40
GND
SLOAD
VTCLK0
CLK0
CLK0
VTCLK0
GND
VTCLK1
CLK1
CLK1
VTCLK1
SDATA
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20 21 22 23 24 25 26
SCLK
Q7
VCC9
VCC8
VCC7
GND
Q9
Q8
Q8
VCC
Q9
Q7
GND
Description
Negative Supply pins must be all externally connected to a power
supply to guarantee proper operation.
Serial Load and Latch control input pin. Defaults LOW when float-
ing open
.
NB4L7210
39 VCC3
38 Q3
37 Q3
36 VCC4
35 Q4
34 Q4
33 GND
32 Q5
31 Q5
30 VCC5
29 Q6
28 Q6
27 VCC6
Figure 2. Pin Configuration
(Top View)
Table 1. PIN DESCRIPTION
Pin
1, 7, 13, 25, 26, 33,
40, 41
2
Name
GND
SLOAD
I/O
Supply
LVCMOS, LVTTL
3, 6, 8, 11
VTCLK0, VTCLK0,
VTCLK1, VTCLK1
CLK0, CLK1
CLK0, CLK1
SDATA
SCLK
VCC, VCC9, VCC8,
VCC7, VCC6, VCC5,
VCC4, VCC3, VCC2,
VCC1, VCC0
Q[9−0]
Q[9−0]
SDATAOUT
EP
Termination−
Internal 50 Ohms Termination Resistor connection Pins. In the
differential configuration when the input termination pins are con-
nected to the common termination voltage.
CLOCK Input (TRUE). If no signal is applied then the device may
be susceptible to self oscillation.
CLOCK Input (INVERT). If no signal is applied then the device
may be susceptible to self oscillation.
Serial Data input pin (for BITS 0:9, a “0” selects CLK1, “1” selects
CLK 0). Defaults LOW when floating open.
Serial Load Clock input pin. Defaults LOW when floating open.
Positive Supply pins must be all externally connected to a power
supply to guarantee proper operation.
4, 9
5, 10
12
14
15, 16, 19, 22, 27,
30, 36, 39, 44, 47,
50, 51
17, 20, 23, 28, 31,
34, 37, 42, 45, 48
18, 21, 24, 29, 32,
35, 38, 43, 46, 49
52
Exposed Pad
Differential LVPECL,
CML, or LVDS
Differential LVPECL,
CML, or LVDS
LVCMOS, LVTTL
LVCMOS, LVTTL
Supply
LVPECL
LVPECL
LVCMOS, LVTTL
GND
Output (INVERT)
Output (TRUE)
Serial Data output pin for cascade
Exposed Pad. The thermally exposed pad (EP) on package bot-
tom (see case drawing) must be attached to a sufficient heat−
sinking conduit for proper thermal operation and must be connec-
ted to GND.
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NB4L7210
10 MUXes
Output Qx
SLOAD
SDATA
SCLK
(A)
10 Bit LATCH
BIT
10 Bit SHIFT
SDATAOUT
9 8 7 6 5 4 3 2 1 0
9 8 7 6 5 4 3 2 1 0
MSB
LSB
SDATA REGISTER DA-
TA BIT VALUE
0 Selects CLK1 / CLK1
1 Selects CLK0 / CLK0
(C)
SDATA 10 BIT REGISTER
10 Bit SHIFT REGISTER
(B)
Figure 3. Serial Data Interface
Table 2. ATTRIBUTES
Characteristic
Input Default State Resistors
ESD Protection
Human Body Model
QFN−52
Value
None
> 2 kV
Level 1
UL 94 V−0 @ 0.125 in
2027
Moisture Sensitivity Pb−Free Package (Note 1)
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
I
I
IN
V
INPP
I
OUT
T
A
T
stg
q
JA
q
JC
T
sol
Positive Power Supply
Positive Input
Input Current Through R
T
(50
W
Resistor)
Differential Input Voltage
Output Current (Q / Q)
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient) (Note 2)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb−Free
0 lfpm
500 lfpm
2S2P (Note 2)
QFN−52
QFN−52
QFN−52
Continuous
Surge
QFN−52
Parameter
Condition 1
GND = 0 V
GND = 0 V
Static
Surge
Condition 2
Rating
6.0
GND−0.3
≤
V
I
≤
V
CC
35
70
2.5
25
50
−40 to +85
−65 to +150
25
19.6
21
265
Unit
V
V
mA
mA
V
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. JEDEC standard 51−6, multilayer board − 2S2P (2 signal, 2 power).
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB4L7210
Table 4. DC CHARACTERISTICS
(V
CC
= 2.375 V to 3.6 V, V
EE
= 0 V, T
A
= −40°C to +85°C (Note 4))
Symbol
I
EED
R
TIN
V
OH
V
OL
I
IH
I
IL
Characteristic
GND Supply Current (All Outputs Loaded)
Internal Input Termination Resistor
Output HIGH Voltage
Output LOW Voltage
Input HIGH Current (VTx/VTx open)
Input LOW Current (VTx/VTx open)
150
Min
110
40
V
CC
−1145
V
CC
−1945
Typ
150
50
V
CC
−1020
V
CC
−1820
8
0.1
Max
200
60
V
CC
−895
V
CC
−1695
150
Unit
mA
W
mV
mV
mA
mA
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED
(Figures 5, 6)
V
th
V
IH
V
IL
V
INAMP
Input Threshold Reference Voltage Range (Note 5)
Single−Ended Input HIGH Voltage
Single−Ended Input LOW Voltage
Single−Ended Input Amplitude
GND +950
V
th
+ 150
GND
300
V
CC
− 150
V
CC
V
th
− 150
V
CC
mV
mV
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(Figures 7, 8)
V
CMR
V
IHD
V
ILD
V
ID
Input Common Mode Range
Differential Input HIGH Voltage
Differential Input LOW Voltage
Differential Input Voltage (V
IHD
− V
ILD
)
GND +950
V
CMR
+ 75
GND
150
V
CC
− 75
V
CC
V
CMR
− 75
2400
mV
mV
mV
mV
LVCMOS/LVTTL INPUTS
(SCLK, SDATA, SLOAD)
V
IH
V
IL
Input HIGH Voltage
Input LOW Voltage
2.0
GND
V
CC
0.8
V
V
LVCMOS/LVTTL OUTPUTS
(SDATAOUT)
V
OH
V
OL
Output HIGH Voltage @ I
OH
= −1.0 mA, R
L
= 20 kW to GND
Output LOW Voltage @ I
OL
= 1.0 mA, R
L
= 20 kW to GND
2.0
3.2
0.25
0.5
V
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
4. Input and Output parameters vary 1:1 with V
CC
. Outputs loaded with 50
W
to V
CC
− 2.0 V (See Figure 16) except SDATAOUT.
5. V
th
is applied to the complementary input when operating in single−ended mode.
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NB4L7210
Table 5. AC CHARACTERISTICS
(V
CC
= 2.375 V to 3.6 V, GND = 0 V, T
A
= −40°C to +85°C (Note 6))
Symbol
V
OUTPP
t
PLH
,
t
PHL
t
SKEW
Characteristic
Output Voltage Amplitude @ V
INPPmin
(See Figure 9)
Propagation Delay to (See Figure 9)
CLK/CLK to Qx/Qx (Note 7)
SCLK to SDATAOUT Measured at 1.5 V
Duty Cycle Skew (Note 8)
Within −Device Skew
Device to Device Skew (Note 8)
Setup Time
SDATA to SCLK Measured at 1.5 V
SCLK to SLOAD+ Measured at 1.5 V
Th
PWmin
t
JIT
(Ø)
Hold Time
Minimum Pulse Width
RMS Phase Jitter, Integration Range 12 KHz to 20 MHz
@155.52 MHz
@ 622.08 MHz
t
JITTER
TIE Rj (10,000 Cycles)
@155.52 MHz
@ 622.08 MHz
Crosstalk RMS Jitter RMS (1000 Cycles) (Note 9)
150
See Fig 10
See Fig 11
1.7
0.63
3.9
750
1200
ps
SDATA to SCLK
SLOAD
−150
1000
325
2.0
−115
345
365
ps
ns
fs
610
6.5
−5
0
0
725
20
2
5
20
875
30.8
10
35
200
ps
ns
ps
f
in
= 100 MHz
f
in
= 1 GHz
Min
650
530
Typ
800
790
Max
875
960
Unit
mV
ts
ps
V
INPP
t
r
, t
f
Input Voltage Swing/Sensitivity
(Differential Configuration, measured Single−ended on each input)
Output Risetime and Falltime
Qx/Qx (20% to 80%)
SDATAOUT (0.8 V − 2.0 V)
mV
120
0.88
185
10
260
15
ps
ns
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
6. Measured by forcing V
INPP
(Typ 750 mV
PP
) from a 50% duty cycle clock source. Q/Q Outputs loaded with 50
W
to V
CC
− 2.0 V (See Figure 16).
SCLK, SDATA and SLOAD at LOW SDATAOUT loaded 20 kW and 15 pF to GND.
7. Measured from the input pair crosspoint to each single output pair crosspoint.
8. Duty cycle skew is measured between differential outputs using the deviations of the sum of T
pw
− and T
pw
+.
9. 155.52 MHz @ 750 mV
PP
input on measured output, 161.13 MHz @ 850 mV
PP
input on all other others.
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