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NB3N3001
3.3 V 106.25 MHz/ 212.5 MHz
PureEdge Clock Generator with
LVPECL Differential Output
Description
The NB3N3001 is a low−jitter, dual−rate PLL−synthesized clock
generator. It accepts a standard 26.5625 MHz fundamental mode AT cut
parallel resonant crystal as the reference source for its integrated crystal
oscillator and low noise phase−locked loop (PLL) and produces user
selectable clock frequencies of either 106.25 MHz or 212.5 MHz.
In addition, the PLL circuitry will generate a 50% duty cycle
square−wave through a pair of differential LVPECL clock outputs.
Typical phase jitter at 106.25 MHz is 0.3 ps RMS from 637 kHz to
10 MHz.
The LVPECL output drivers can be disabled to high impedance with
the OE pin set LOW. The NB3N3001 operates from a single +3.3 V
supply, and is available in both plastic package and die form. The
operating temperature range is from
−40°C
to +85°C.
The NB3N3001 device provides the optimum combination of low
cost, flexibility, and high performance which makes it ideal for
Fibre−Channel applications.
Features
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MARKING
DIAGRAM
301
YWW
AG
TSSOP−8
DT SUFFIX
CASE 948S
A
Y
WW
G
= Assembly Location
= Year
= Work Week
= Pb−Free Package
•
•
•
•
•
•
•
•
•
•
•
•
PureEdge Clock Family Provides Accuracy and Precision
Selectable Output Frequency of 106.25 MHz or 212.5 MHz
Crystal Oscillator Interface Designed for a 26.5625 MHz Crystal
Fully Integrated Phase−Lock−Loop with Internal Loop Filter
Differential 3.3 V LVPECL Outputs
Exceeds Bellcore and ITU Jitter Generation Specification
RMS Phase Jitter @ 106.25 MHz, using a 26.5625 MHz Crystal
(637 kHz
−
10 MHz): 0.3 ps (Typical)
RMS Phase Noise at 106.25 MHz
Phase Noise:
Offset Noise Power
100 Hz
−108
dBc/Hz
1 kHz
−122
dBc/Hz
10 kHz
−135
dBc/Hz
100 kHz
−135
dBc/Hz
Operating Range: V
CC
= 3.135 V to 3.465 V
−40°C
to +85°C Ambient Operating Temperature
Small Footprint 8−pin TSSOP Package
This is a Pb−Free Device
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
FSEL
X
IN
Q
26.5625 MHz
X
OUT
Crystal
Oscillator
Phase
Detector
Charge
Pump
M =
B32
VCO
850 MHz
N =B8
orB4
LVPECL
Output
212.5 MHz
or
Q 106.25 MHz
Figure 1. Logic Diagram
©
Semiconductor Components Industries, LLC, 2008
August, 2008
−
Rev. 2
1
Publication Order Number:
NB3N3001/D
NB3N3001
VCCA
VEE
XOUT
XIN
1
2
8
7
VCC
Table 1. Output Frequency Select
Q
Q
FSEL
FSEL
0
1
NOTE: Input crystal = 26.5625 MHz
Output Frequency (MHz)
106.25
212.5
NB3N3001
3
4
6
5
Figure 2. Pinout (Top View)
Table 2. PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
Symbol
V
CCA
V
EE
X
OUT
X
IN
FSEL
Q
Q
V
CC
Type
Power
Power
Input
Input
LVTTL/LVCMOS
Input
Output
Output
Power
Description
Positive analog power supply pin. Connected to V
CC
with filter components (See Figure 8).
Negative supply pin.
Crystal input (OUT).
Crystal input (IN).
Frequency select pin. Defaults LOW when left open. Internal pull down resistor to V
EE
.
Inverted differential output. Typically terminated with 50
W
to V
CC
−2.0
V.
Noninverted differential output. Typically terminated with 50
W
to V
CC
−2.0
V.
Positive digital core power supply pin. Connected to 3.3 V.
Table 3. ATTRIBUTES
Characteristic
ESD Protection
Moisture Sensitivity (Note 1)
Human Body Model
Machine Model
Pb−Free Pkg, TSSOP−8
Value
> 6 kV
> 200 V
Level 3
UL 94 V−0 @ 0.125 in
4150
Flammability Rating Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
I
I
O
q
JA
T
STG
Supply Voltage
Inputs
Output Current
Thermal Resistance (Junction−to−Ambient)
Storage Temperature
Continuous
Surge
0 Lfpm
500 Lfpm
Parameter
Value
4.6
−0.5
to V
CC
+ 0.5
50
100
142
103
−65
to 150
Unit
V
V
mA
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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2
NB3N3001
Table 5. POWER SUPPLY DC CHARACTERISTICS,
(V
CC
= 3.3 V
±5%,
T
A
=
−40°C
to 85°C
)
Symbol
V
CC
V
CCA
I
CCA
I
EE
Parameter
Core Supply Voltage
Analog Supply Voltage
Analog Supply Current
Power Supply Current
Included in I
EE
Conditions
Min
3.135
3.135
Typ
3.3
3.3
19
27
Max
3.465
3.465
23
31
Unit
V
V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 6. LVPECL DC CHARACTERISTICS,
(V
CC
= 3.3 V
±5%,
T
A
=
−40°C
to 85°C
)
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage (Note 2)
Output Low Voltage (Note 2)
Peak−to−Peak Output Voltage Swing
Conditions
Min
V
CC
−
1.4
V
CC
−
2.0
0.6
0.75
Typ
Max
V
CC
−
0.9
V
CC
−
1.7
1.0
Unit
V
V
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Outputs terminated with 50
W
to V
CC
−
2.0 V. See Figures 4 and 12.
Table 7. LVTTL/LVCMOS DC CHARACTERISTICS,
(V
CC
= 3.3 V
±5%,
T
A
=
−40°C
to 85°C
)
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
FSEL
FSEL
V
CC
= V
IN
= 3.465 V
V
CC
= 3.465 V, V
IN
= 0 V
−5.0
Conditions
Min
2.0
−0.3
Typ
Max
V
CC
+ 0.3
0.8
150
Unit
V
V
mA
mA
Table 8. PIN CHARACTERISTICS
Symbol
C
IN
R
PD
Parameter
Input Capacitance
Input Pull Down Resistor
Conditions
Min
Typ
4
100
Max
Unit
pF
kW
Table 9. CRYSTAL CHARACTERISTICS
(Fundamental Mode 18 pF Parallel Resonant Crystal
)
Parameter
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Conditions
Min
Typ
26.5625
50
7.0
Max
Unit
MHz
W
pF
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3
NB3N3001
Table 10. AC CHARACTERISTICS,
(V
CC
= 3.3 V
±5%,
T
A
=
−40°C
to 85°C (Note 4))
Symbol
f
OUT
t
jit(∅)
Parameter
Output Frequency
RMS Phase Jitter (Random)
(Note 3)
Conditions
24 MHz
−
30 MHz Crystal
(Typ. 25 MHz
−
26.5625 MHz)
106.25 MHz; Integration Range:
637 kHz
−10
MHz
212.5 MHz; Integration Range:
637 kHz
−10
MHz
t
R
/t
F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80% (See Figure 7)
(See Figure 6)
275
48
Min
Typ
106.25/
212.5
0.3
0.3
600
52
ps
%
Max
Unit
MHz
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Please refer to the Phase Noise Plot.
4. Output terminated with 50
W
to V
CC
−
2.0 V. See Figures 4 and 12.
NOISE POWER (dBc)
OFFSET FREQUENCY (Hz)
Figure 3. Typical Phase Noise at 106.25 MHz
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