LX1689
TM
®
Third Generation CCFL Controller
P
RODUCTION
D
ATA
S
HEET
DESCRIPTION
KEY FEATURES
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OM
The LX1689 is the latest generation
Direct Drive CCFL (Cold Cathode
Fluorescent Lamp) Controller. It uses
new circuit design techniques (patents
pending) and combines digital and linear
circuits with an advanced BiCMOS
process to create a more complete
controller in a small package.
When compared to the original
LX1686 design, identical module
applications use from 12 to 30 less
components. New functions and
enhancements have been added to make
the LX1689 even easier to use.
The on-chip PLL circuit used to
synchronize the digital dimming burst
frequency to the video frame rate, as
used in the LX1686, is replaced with a
programmable counter. This counter can
divide the video controller horizontal
sync pulse, other external clock source
or the internal chip clock source to
generate the burst frequency.
The brightness control input allows the
use of either a DC voltage or a PWM
input to simplify design. Programmable
polarity brightness control is retained,
except in the case of externally clocked
digital dimming. Two onboard LDO
regulators extend the input voltage range
of the IC up to 28 Volts without using
external circuitry as was required with our
previous controllers.
The LX1689
includes a new lamp strike detection
scheme that saves a package pin and three
external components. Internal circuits
monitor lamp current pulses at the I_SNS
input to determine if the lamp strikes and
if it stays ignited once operational.
Integrating full wave rectifiers for
each of three lamp inputs has significantly
reduced the lamp feedback component
count. In addition the controller features
include auto shutdown for open or broken
lamps, and a lamp fault detection with a
status reporting output.
3 to 28 Volt Single Fixed (±20%)
Supply Operating Range
Selectable Analog/Digital
Dimming Modes
Digital Dimming Can Synch to
External Or Internal Clocks
User Programmable Digital
Dimming Burst Frequency
252 mS Power On Delay
Flexible Lamp Current
Compensation Input
Open Lamp Shutdown and Fault
Output Indicator
“On Chip” Full Wave Lamp
Current & Voltage Rectifiers
20 Pin TSSOP Package
BENEFITS
Low Component Count /
Module Cost / Size
High “Nits/Watt” Efficiency
Operates Directly From 1 to 6
Li_Ion Cells
Lamp Current Compensation
Input Makes Indoor/Outdoor
And Wide Temperature Range
Applications Easy to Design
IMPORTANT:
For the most current data, consult
MICROSEMI’s
website:
http://www.microsemi.com
Protected By U.S. Patents: 5,615,093; 5,923,129; 5,930,121; 6,198,234; Patents Pending
PRODUCT HIGHLIGHT
LX1689 CCFL Inverter Layouts Examples*
2.64in.
(67mm)
.397 in
.
(10mm)
Actual Inverter Size
OR
1.38in.
(35mm)
.870 in.
(22mm)
Actual Inverter Size
*As Shown in Figure 1 (Typical Application)
Bill of Materials
1
LX1689CPW
1
Transformer
1
Dual FET
2
Connectors
7
Resistors
9
Capacitors
21
Total Count
LX1689
LX1689
PACKAGE ORDER INFO
T
J
(°C)
0 to 70
-40 to 85
M
IN
V
DD
3V
3V
M
AX
V
DD
28V
28V
PW
Plastic TSSOP
20-PIN
LX1689CPW
LX1689IPW
RoHS Compliant / Pb-free Transition DC: 0442
Note: Available in Tape & Reel. Append the letters “TR” to the part number. (i.e. LX1689CPW-TR)
Copyright
©
2000
Rev. 1.1, 2006-02-27
Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 1
LX1689
TM
®
Third Generation CCFL Controller
P
RODUCTION
D
ATA
S
HEET
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (
V
_BATT
)................................................................................................. 30V
Digital Input (
ENABLE
).....................................................................................-0.3V to 7V
Analog Inputs Transient Peak (
I_SNS, OC_SNS, OV_SNS)
..............................-25V to +25V
Analog Inputs (
BRITE_IN, EA_IN
).................................................................. -0.3V to 5.5V
Digital Inputs (DIM_CLK,
DIM_MODE, DIV_248
) ......................................... -0.3V to 5.5V
Digital Output (
A
OUT
, B
OUT
) .................................................................-0.3V to V
DD_P
+0.5V
Analog Outputs (
BRITE_C, I_R, BRITE_OUT, BRITE_R, EA_OUT
) ...-0.3V to V
DD_A_
+0.5V
Storage Temperature Range ........................................................................ -65°C to 150°C
Maximum Operating Junction Temperature...............................................................150°C
RoHS / Pb-free Peak Package Solder Reflow Temperature
(40 second maximum exposure).....................................................................260°C (+0,-5)
Note:
Exceeding these ratings could cause damage to the device. All voltages are with respect to
Ground. Currents are positive into, negative out of specified terminal.
PACKAGE PIN OUT
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GND
A
OUT
B
OUT
DIM_CLK
DIM_MODE
DIV_248
BRITE_C
BRITE_R
BRITE_IN
ENABLE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD_P
VDD_A
V_BATT
OC_SNS
OV_SNS
I_SNS
BRITE_OUT
EA_OUT
EA_IN
I_R
PW P
ACKAGE
(Top View)
RoHS / Pb-free 100% Matte Tin Lead Finish
THERMAL DATA
PW
Plastic TSSOP 20-Pin
144°C/W
T
HERMAL RESISTANCE
-
JUNCTION TO
A
MBIENT
,
θ
JA
Junction Temperature Calculation: T
J
= T
A
+ (P
D
x
θ
JA
).
The
θ
JA
numbers are guidelines for the thermal performance of the device/pc-board
system. All of the above assume no ambient airflow.
FUNCTIONAL PIN DESCRIPTION
P
IN
N
AME
GND
Ground
Power VDD_P Supply Output. This output pin is used to connect an external capacitor to stabilize and filter the
on chip VDD_P LDO regulator. The input of the LDO is the switched V
_BATT
supply. LDO output is normally 5.3V
and is used only to drive the output buffers at A
OUT
and B
OUT
. The external capacitor will be a 100 to 1000nF
ceramic dielectric. Up to 5mA DC additional load may be imposed by external circuitry. External load must be
reduced if the combination of output current and input voltage exceeds power dissipation capability of the die.
A buffer N-FET driver output. The pin includes a internal 10K pull down resistor.
Analog VDD_A Supply Output. This output pin is used to connect an external capacitor to stabilize and filter the
on chip VDD_A LDO regulator. The input of the LDO is the switched V
_BATT
supply. LDO output is normally
2.95V and is used to drive all circuitry except the output buffers at AOUT and BOUT. Average internal load is
6mA. Up to 5mA DC additional load may be imposed by external circuitry. External load must be reduced if the
combination of output current and input voltage exceeds power dissipation capability of the die. The external
capacitor will be a 100 to 1000nF ceramic dielectric type.
B buffer N-FET driver output. The pin includes a internal 10K pull down resistor.
Voltage Input, 3 to 28V input range. V
_BATT
is switched (see ENABLE) to remove power from chip. Two LDO
regulators follow the switch, one generates VDD_P (see VDD_P) and the other VDD_A (see VDD_A). Care
must be taken in power distribution design to minimize transients and noise coupling from the VDD_P output to
the VDD_A output. The external capacitor will be a 100 to 1000nF ceramic dielectric type.
D
ESCRIPTION
V
DD_P
A
OUT
V
DD_A
P
ACKAGE
D
ATA
P
ACKAGE
D
ATA
B
OUT
V
_BATT
Copyright
©
2000
Rev. 1.1, 2006-02-27
Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 2
LX1689
TM
®
Third Generation CCFL Controller
P
RODUCTION
D
ATA
S
HEET
FUNCTIONAL PIN DESCRIPTION
(CONTINUED)
P
IN
N
AME
D
ESCRIPTION
Digital Dimming Clock / Dimming Polarity. An input pin that may be selected to control burst frequency for
external Digital Dimming. This input can be any clock signal up to 200KHz. This pin is also used to control the
dimming polarity when operating in the analog or internal digital mode. If DIM_MODE is in the open condition
(Analog Dimming Mode) the DIM_CLK input should be connected to VDD_A for conventional dimming polarity
or set to Ground for reverse polarity. Conventional polarity means that lamp brightness increases with
increasing voltage on the BRITE_IN pin. Reverse polarity means that brightness decreases with increasing
voltage.
Over Current Sense Input. A full wave AC voltage input centered on ground that is proportional to total high
voltage transformer secondary winding current. The OC_SNS input is full wave rectified, then applied to a digital
comparator with a 2V reference to cause peak voltages greater than 2V to digitally reset the PWM logic on a
pulse by pulse basis.
Frequency range of the input signal is 10kHz to 500KHz. Normal operating voltage levels should be under
max ±1.8VPK, and abnormal voltage can operate continuously as high as ± 10V peak under load fault
conditions. Transients under fault conditions can reach ± 25VPK.
Dimming Mode Input. This three state input pin places the IC in Analog Dimming Mode, internal Digital Dimming
Mode, or external Digital Dimming Mode. If the input is left open or forced to VDD_A / 2 Analog mode is
selected.
If connected to VDD_A, Digital Dimming with a external clock source applied to the DIM_CLK input is
selected to the burst timing generator. If connected to Ground, Digital Dimming with a internal clock is selected.
The internal clock is equivalent to the frequency at AOUT divided by two, both the internal or external clock
frequency can be divided down by setting the DIV_248 pin. (see DIV_248)
Over Voltage Sense Input. A full wave AC voltage input centered around ground that is proportional to lamp
voltage. The OV_SNS input will be full wave rectified, then applied to a digital comparator with a 2V reference to
cause peak voltage greaten than 2V to digitally reset the PWM logic on a pulse by pulse basis.
Frequency range of the input signal is 10Khz to 500KHz. Normal operating voltage levels should be under
±1.8VPK, and abnormal voltage can operate continuously as high as ±10V peak under load fault conditions.
Transients under fault conditions can reach ± 25VPK.
The input has a 10K pull down resistor that serves as a DC restorer to the external capacitor that divides
down lamp voltage.
Divide Digital Dimming clock by 2, 4, or 8. This three state input pin causes the internal or external digital
dimming clock source to be divided by one of the three values, 2, 4, or 8. Its purpose is to allow a selection of
three possible burst rates for any given external or internal clock source. A high (VDD_A) selects divide by 2,
open selects divide by 4, and ground selects divided by 8. We advise keeping burst above 95Hz and below
about 400HZ. This will minimize visible flicker and possible audible noise from the power supply components.
Current Sense Input. A full wave AC voltage input centered around ground that is proportional to lamp current.
The I_SNS input is full wave rectified and amplified, then presented to the inverting input of the current error
amplifier through a 100K resistor.
Frequency range of the input signal is 10KHz to 500KHz. Normal operating voltage levels will be in the range
of ± 0.5 to 2.5VPK, and abnormal voltage can operate continuously as high as ± 10V peak under load fault
conditions. Transient under fault conditions can reach ± 25VPK. We strongly recommend a 10K resistor be
placed in series with the pin to limit current from voltage spikes that can occur by intermittent lamp connectors,
or arcing from a faulty high voltage transformer. This resistor will eliminate the possibility of IC damage under
these fault conditions.
The open lamp fault logic monitors the I_SNS pin voltage and number of lamp current cycles. If the number
of lamp current cycles with amplitude below fault threshold are less than 8 in a given fault checking period then
the strike latch will not be reset and a fault is declared, which shuts down the A/B outputs. In the strike mode, if
no lamp current is detected after 15 attempts a fault is likewise declared. ( See further LX1689 operation
section)
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DIM_CLK
OC_SNS
DIM_MODE
OV_SNS
DIV_248
P
ACKAGE
D
ATA
P
ACKAGE
D
ATA
I_SNS
Copyright
©
2000
Rev. 1.1, 2006-02-27
Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 3
LX1689
TM
®
Third Generation CCFL Controller
P
RODUCTION
D
ATA
S
HEET
FUNCTIONAL PIN DESCRIPTION
(CONTINUED)
P
IN
N
AME
D
ESCRIPTION
BRITE Filter Capacitor and FAULT Output. Used to convert higher frequency digital PWM inputs to proportional
DC currents at the BRITE_OUT pin. The capacitor forms a low pass filter with an internal 200K resistor. This
pin will be driven to VDD_A if a lamp fault is detected by the LX1689. If no fault is present the voltage at this pin
will vary from 50mV to 1.05V as BRITE_IN varies from 0 to 2V. A CMOS gate may be connected to this pin to
sense the fault condition. TTL gates or other low impedance (less than 20 megohm) must not be connected to
this node as their DC resistance will load the internal 200K resistor and create error in the BRITE_OUT current
level.
Error Amp Inverting Input. Frequency Compensation input for the Error Amplifier. See EA_OUT below. A
100K, negative TC on chip resistor connected between the inverting input of the error amplifier and the output of
the I_SNS full wave rectifier is the resistor in an R/C loop compensation network.
Dedicated Bias resistor for BRITE_OUT current source.
Error Amp Output. Error amplifier is a GM type and does not require a external capacitor for stability. An
external capacitor is connected from this pin to EA_IN to adjust the loop response of the inverter module. This
capacitor value can vary from 100pF to 5000pF in various applications. This capacitor may also be connected
from the EA_OUT to ground.
Brightness Control Input. The input signal can be a DC voltage, a low frequency pulse width modulated digital
signal, or a high frequency pulse width modulated digital signal. Active DC voltage range is 0.5 to 2.0V. Signals
above 2V are clipped and signals below 0.5V make output current from the BRITE_OUT pin near zero. Low
frequency digital PWM signals up to 500Hz can be applied to affect Digital Dimming. Higher frequency PWM
signals, up to 100KHz are filtered to an equivalent DC current at the BRITE_OUT pin by adding a capacitor at
the BRITE_C pin. On chip signal conditioning amplifiers clip inputs above 2V so that lamp current amplitude is
not sensitive to the voltage level variations of a digital PWM input signal.
Brightness Reference Current Output. This variable current source is the mirror of BRITE_R current multiplied
by the voltage at BRITE_C (0 to 1.0V) when analog dimming is selected, or by 1.0V when digital dimming is
selected. It becomes the reference voltage to the lamp current error amplifier when applied to an external
precision resistor connected from the BRITE_OUT pin to ground. BRITE_OUT current:
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BRITE_C
EA_IN
BRITE_R
EA_OUT
BRITE_IN
I
BRITE_OUT
=
I
BRITE_R
×
1.0 (Digital Dimming Mode)
BRITE_OUT
I
BRITE_OUT
=
I
BRITE_R
×
V
BRITE_C
(Analog Dimming Mode)
V
BRITE_OUT
=
I
BRITE_R
×
R
BRITE_OUT
I
BRITE_R
=
1.00V
R
BRITE_R
ENABLE
Chip Enable Input. If logic high, all functions are enabled. If logic low, internal power is disconnected from the
V
_BATT
pin, disabling all functions. Logic threshold is about 1.2V. Maximum current into V_BATT when
ENABLE < 0.3V, V_BATT <28V, is 28 µA. ENABLE may be connected to V_BATT through a series resistor if
the disable function is not used. Resistor tolerance is ± 10%; and R value is:
[V_BATT
MIN
−
1.5V]
R
=
−
6
30x10 Amp
The Enable pin can be connected directly to 3.3/5V logic.
Current Reference Resistor Input. Connects to an external resistor that determines the magnitude of internal
bias currents. The nominal lamp frequency can be adjusted by varying this resistor value in the range of 10K to
150K Ohms.
1.00V
I
I_R
=
R
I_R
P
ACKAGE
D
ATA
P
ACKAGE
D
ATA
I_R
Copyright
©
2000
Rev. 1.1, 2006-02-27
Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 4
LX1689
TM
®
Third Generation CCFL Controller
P
RODUCTION
D
ATA
S
HEET
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (V
_BATT
)
Digital Input (ENABLE)
Analog Inputs (I_SNS, OC_SNS, OV_SNS)
BRITE_IN Linear DC Voltage Range
BRITE_IN PWM Logic Signal Voltage Range
Digital Inputs (DIM_MODE, DIV_248,DIM_CLK)
Maximum Output Gate Charge (A
OUT
, B
OUT
)
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Min
3
0
-3
0.5
0
0
LX1689
Typ
Max
28
6.5
3
2
5
5.5
Units
V
V
V
PK
V
V
V
nC
10
20
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, the following specifications apply over the operating ambient temperature: LX1689CPW: 0
°
C
≤
T
A
≤
70
°
C,
LX1689IPW: -40°C
≤
T
A
≤
85°C, except where otherwise noted.
Test conditions: V_BATT =3.3 to 28 V
DC
, I_R =80.6K
Ω
, BRITE_R = BRITE_OUT = 10K
Ω
, BRITE_C =open, ICOMP =100pf
Parameter
POWER
Regulator Output Voltage
V
DD_P
Drop Out Voltage
Regulator Output Voltage
V
DD_A
Dropout Voltage
V
BATT
Static Current
V
BATT
Dynamic Current
Sleep Mode Current
Sleep Mode Current
ENABLE INPUT
Run Threshold
Shutdown Threshold
Input High Current
Input High Current
Input Low Current
UNDER VOLTAGE LOCKOUT
Startup Threshold
UVLO Threshold
UVLO Hysteresis
V
T_UVLO
V
H_UVLO
Run Mode
Shutdown Mode
2.1
2.55
2.35
200
2.8
V
V
mV
V
TH_ENRUN
V
TL_ENSHDN
I
IH_ENABLE
I
IH_ENABLE
I
IL_ENABLE
ENABLE = 2V
ENABLE = 5V
ENABLE = 0V
-1
0.4
1.1
1.1
2
35
0
12
80
1
1.4
V
V
µA
µA
µA
V
DD_P
∆V
DD_P
V
DD_A
∆V
DD_A
I
BATT
I
BATT
I
BATT_SLEEP
I
BATT_SLEEP
C
AOUT
= C
BOUT
= 1000pF
V
ENABLE
≤
0.4V; V
BATT
= 5V
V
ENABLE
≤
0.4V; V
BATT
= 28V
V
_BATT
= 6 to 28 V, I Load = 0 – 5mADC
∆V
DD_P
= -1% , I Load = 5mADC; T
A
= 25°C
V
_BATT
= 3.5 to 28V, I Load = 0 – 5mADC
∆V
DD_A
= -1% , I Load = 5mADC; T
A
= 25°C
2.75
5.05
5.3
50
2.95
100
5.5
10
2.8
22
9
17
5
35
3.15
5.55
V
mV
V
mV
mA
mA
µA
µA
Symbol
Test Conditions
Min
LX1689
Typ
Max
Units
E
LECTRICALS
E
LECTRICALS
Copyright
©
2000
Rev. 1.1, 2006-02-27
Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 5
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