N25Q128A23T1240E datasheet, PDF

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N25Q128A23T1240E: Description16M X 8 FLASH 3V PROM, PBGA24; Categorystorage; File Size5MB，180 Pages; ManufacturerNumonyx ( Micron ); Websitehttps://www.micron.com

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N25Q128A23T1240E Overview

16M X 8 FLASH 3V PROM, PBGA24

N25Q128A23T1240E Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	24
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	3.6 V
Minimum supply/operating voltage	2.7 V
Rated supply voltage	3 V
maximum clock frequency	108 MHz
Processing package description	6 × 8 MM, ROHS COMPLIANT, TBGA-24
Lead-free	Yes
EU RoHS regulations	Yes
state	ACTIVE
packaging shape	Rectangle
Package Size	GRID array, THIN PROFILE
surface mount	Yes
Terminal form	BALL
Terminal spacing	1 mm
terminal coating	tin silver copper
Terminal location	BOTTOM
Packaging Materials	Plastic/Epoxy
Temperature level	INDUSTRIAL
memory width	8
organize	16M × 8
storage density	1.34E8 deg
operating mode	Synchronize
Number of digits	1.68E7 words
Number of digits	16M
Memory IC type	FLASH 3V programmable read-only memory
serial parallel	serial

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N25Q128

128-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase on boot sectors,

XiP enabled, serial flash memory with 108 MHz SPI bus interface

Features

SPI-compatible serial bus interface

108 MHz (maximum) clock frequency

2.7 V to 3.6 V single supply voltage

Supports legacy SPI protocol and new Quad

I/O or Dual I/O SPI protocol

Quad/Dual I/O instructions resulting in an

equivalent clock frequency up to 432 MHz:

XIP mode for all three protocols

– Configurable via volatile or non-volatile

registers (enabling

the memory to work in

XiP mode directly after power on)

Program/Erase suspend instructions

Continuous read of entire memory via single

instruction:

– Fast Read

– Quad or Dual Output Fast Read

– Quad or Dual I/O Fast Read

Flexible to fit application:

– Configurable number of dummy cycles

– Output buffer configurable

– Fast POR instruction to speed up power on

phase

– Reset function available upon customer

request

64-byte user-lockable, one-time programmable

(OTP) area

Erase capability

– Subsector (4-Kbyte) granularity in the 8

boot sectors (bottom or top parts).

– Sector (64-Kbyte) granularity

Write protections

– Software write protection applicable to

every 64-Kbyte sector (volatile lock bit)

– Hardware write protection: protected area

size defined by five non-volatile bits (BP0,

BP1, BP2, BP3 and TB bit)

VDFPN8 (F8)

8 × 6 mm (MLP8)

SO16 (SF)

300 mils width

TBGA24 (12)

6 x 8 mm

– Additional smart protections available upon

customer request

Electronic signature

– JEDEC standard two-byte signature

(BA18h)

– Additional 2 Extended Device ID (EDID)

bytes to identify device factory options

– Unique ID code (UID) with 14 bytes read-

only, available upon customer request

More than 100,000 program/erase cycles per

sector

More than 20 years data retention

Packages

– RoHS compliant

February 2010

Rev 1.0

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Contents

M25Q128 - 3 V

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

Serial data output (DQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Serial data input (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Hold (HOLD) or Reset (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Write protect/enhanced program supply voltage (W/VPP), DQ2 . . . . . . . 18

supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

SPI Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1

4.2

4.3

Extended SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Dual I/O SPI (DIO-SPI) protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Quad SPI (QIO-SPI) protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1

Extended SPI Protocol Operating features . . . . . . . . . . . . . . . . . . . . . . . 23

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

5.1.8

5.1.9

5.1.10

Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Dual input fast program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Dual Input Extended Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Quad Input Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Quad Input Extended Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Subsector erase, sector erase and bulk erase . . . . . . . . . . . . . . . . . . . 24

Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . 24

Active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . 25

Hold (or Reset) condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2

Dual SPI (DIO-SPI) Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.2.1

Multiple Read Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

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M25Q128 - 3 V

5.2.2

5.2.3

5.2.4

5.2.5

5.2.6

5.2.7

5.2.8

Contents

Dual Command Fast reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Subsector Erase, Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . 28

Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . 28

Read and Modify registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . 28

HOLD (or Reset) condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.3

Quad SPI (QIO-SPI)Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

5.3.7

5.3.8

5.3.9

Multiple Read Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Quad Command Fast reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

QUAD Command Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Subsector Erase, Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . 30

Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . 30

Read and Modify registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . 31

HOLD (or Reset) condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

VPP pin Enhanced Supply Voltage feature . . . . . . . . . . . . . . . . . . . . . . 31

Volatile and Non Volatile Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.1

Legacy SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5

WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

BP3, BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

TB bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.2

Non Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.2.1

6.2.2

6.2.3

6.2.4

6.2.5

6.2.6

6.2.7

Dummy clock cycle NV configuration bits (NVCR bits from 15 to 12) . . 37

XIP NV configuration bits (NVCR bits from 11 to 9) . . . . . . . . . . . . . . . . 38

Output Driver Strength NV configuration bits (NVCR bits from 8 to 6) . . 38

Fast POR NV configuration bit (NVCR bit 5) . . . . . . . . . . . . . . . . . . . . . 38

Hold (Reset) disable NV configuration bit (NVCR bit 4) . . . . . . . . . . . . 38

Quad Input NV configuration bit (NVCR bit 3) . . . . . . . . . . . . . . . . . . . . 38

Dual Input NV configuration bit (NVCR bit 2) . . . . . . . . . . . . . . . . . . . . . 39

6.3

Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.3.1

6.3.2

Dummy clock cycle: VCR bits 7 to 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

XIP Volatile Configuration bits (VCR bit 3) . . . . . . . . . . . . . . . . . . . . . . . 41

6.4

Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . 41

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Contents

6.4.1

6.4.2

6.4.3

6.4.4

6.4.5

M25Q128 - 3 V

Quad Input Command VECR<7> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Dual Input Command VECR<6> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Reset/Hold disable VECR<4> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Accelerator pin enable: QIO-SPI protocol / QIFP/QIEFP VECR<3> . . . 43

Output Driver Strength VECR<2:0> . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6.5

Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.5.1

6.5.2

6.5.3

6.5.4

6.5.5

6.5.6

6.5.7

P/E Controller Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Erase Suspend Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Erase Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Program Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

VPP Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Program Suspend Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Protection Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.1

7.2

SPI Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Specific hardware and software protection . . . . . . . . . . . . . . . . . . . . . . . . 48

Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

9.1

Extended SPI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

9.1.1

9.1.2

9.1.3

9.1.4

9.1.5

9.1.6

9.1.7

9.1.8

9.1.9

9.1.10

9.1.11

9.1.12

9.1.13

9.1.14

9.1.15

Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . 81

Dual Output Fast Read (DOFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Dual I/O Fast Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Quad Output Fast Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Quad I/O Fast Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Read OTP (ROTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Dual Input Fast Program (DIFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Dual Input Extended Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Quad Input Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Quad Input Extended Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

4/180

M25Q128 - 3 V

9.1.16

9.1.17

9.1.18

9.1.19

9.1.20

9.1.21

9.1.22

9.1.23

9.1.24

9.1.25

9.1.26

9.1.27

9.1.28

9.1.29

9.1.30

9.1.31

9.1.32

9.1.33

Contents

Program OTP instruction (POTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Subsector Erase (SSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Program/Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Program/Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Write status register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Read Lock Register (RDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Write to Lock Register (WRLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Read Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Clear Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Read NV Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Write NV Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Read Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Write Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Read Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . 110

Write Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . 110

9.2

DIO-SPI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

9.2.1

9.2.2

9.2.3

9.2.4

9.2.5

9.2.6

9.2.7

9.2.8

9.2.9

9.2.10

9.2.11

9.2.12

9.2.13

9.2.14

9.2.15

9.2.16

9.2.17

9.2.18

Multiple I/O Read Identification protocol . . . . . . . . . . . . . . . . . . . . . . . 113

Dual Command Fast Read (DCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Read OTP (ROTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Dual Command Page Program (DCPP) . . . . . . . . . . . . . . . . . . . . . . . 116

Program OTP instruction (POTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Subsector Erase (SSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Program/Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Program/Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Write status register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Read Lock Register (RDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Write to Lock Register (WRLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Read Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Clear Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

5/180

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Please help me answer some questions about C6678 multi-core startup: I haven't got the board yet, and now I want to understand some questions. I hope you can give me some advice. 1. Regarding the order of c6678 multi-core startup, I have read some information. After po...; guzl86 DSP and ARM Processors

AVR chip locked, help needed: Today I used ISp to download atmega16, and the chip seemed to be locked. I used progisp software. After I bought a new chip, I soldered an Atmega16 and 51 on the same board, using the same power suppl...; jialaolian Microchip MCU

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