NCP3420
MOSFET Driver with Dual
Outputs for Synchronous
Buck Converters
The NCP3420 is a single Phase 12 V MOSFET gate driver
optimized to drive the gates of both high−side and low−side power
MOSFETs in a synchronous buck converter. The high−side and
low−side driver is capable of driving a 3000 pF load with a 30 ns
propagation delay and a 20 ns transition time.
With a wide operating voltage range, high or low side MOSFET
gate drive voltage can be optimized for the best efficiency. Internal
adaptive nonoverlap circuitry further reduces switching losses by
preventing simultaneous conduction of both MOSFETs.
The floating top driver design can accommodate VBST voltages as
high as 35 V, with transient voltages as high as 40 V. Both gate outputs
can be driven low by applying a low logic level to the Output Disable
(OD) pin. An Undervoltage Lockout function ensures that both driver
outputs are low when the supply voltage is low, and a Thermal
Shutdown function provides the IC with overtemperature protection.
Features
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MARKING
DIAGRAMS
8
8
1
SO−8
D SUFFIX
CASE 751
3420
ALYW
G
8
1
1
1
A
L
Y
W
G
DFN8
MN SUFFIX
CASE 506BJ
3420
ALYWG
G
•
Thermal Shutdown for System Protection
•
Internal Pulldown Resistor Suppresses Transient Turn On of Either
•
•
•
•
•
•
•
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
MOSFET
Anti Cross−Conduction Protection Circuitry
One Input Signal Controls Both the Upper and Lower Gate Outputs
Output Disable Control Turns Off Both MOSFETs
Complies with VRM10.x and VRM11.x Specifications
Undervoltage Lockout
Thermally Enhanced Package Available
These are Pb−Free Devices
PIN CONNECTIONS
BST
IN
OD
V
CC
1
BST
IN
OD
V
CC
(Top View)
8
DRVH
SWN
PGND
DRVL
1
8
DRVH
SWN
PGND
DRVL
ORDERING INFORMATION
Device
NCP3420DR2G
NCP3420MNR2G
Package
SO−8
(Pb−Free)
DFN8
(Pb−Free)
Shipping
†
2500 Tape & Reel
3000 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2009
December, 2009
−
Rev. 3
1
Publication Order Number:
NCP3420/D
NCP3420
OD
3
V
CC
TSD
UVLO
IN
2
8
DRVH
1
BST
FALLING
EDGE
DELAY
FALLING
EDGE
DELAY
START
STOP
NON−OVERLAP
TIMERS
MONITOR
7
MONITOR
SWN
MIN DRVL
OFF TIMER
4
5
6
V
CC
DRVL
PGND
Figure 1. Block Diagram
PIN DESCRIPTION
SO−8
1
DFN8
1
Symbol
BST
Description
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds
this bootstrap voltage for the high−side MOSFET as it is switched. The recommended capacitor value
is between 100 nF and 1.0
mF.
An external diode is required with the NCP3420.
Logic−Level Input. This pin has primary control of the drive outputs.
Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low.
Input Supply. A 1.0
mF
ceramic capacitor should be connected from this pin to PGND.
Output drive for the lower MOSFET.
Power Ground. Should be closely connected to the source of the lower MOSFET.
Switch Node. Connect to the source of the upper MOSFET.
Output drive for the upper MOSFET.
2
3
4
5
6
7
8
2
3
4
5
6
7
8
IN
OD
V
CC
DRVL
PGND
SWN
DRVH
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2
NCP3420
MAXIMUM RATINGS
Rating
Operating Ambient Temperature, T
A
Operating Junction Temperature, T
J
(Note 1)
Package Thermal Resistance: SO−8
Junction−to−Case, R
qJC
Junction−to−Ambient, R
qJA
(2−Layer Board)
Package Thermal Resistance: DFN8 (Note 2)
Junction−to−Case, R
qJC
(From die to exposed pad)
Junction−to−Ambient, R
qJA
Storage Temperature Range, T
S
Lead Temperature Soldering (10 sec): Reflow (SMD styles only)
JEDEC Moisture Sensitivity Level
Pb−Free (Note 3)
SO−8 (260 peak profile)
Value
0 to 85
0 to 150
45
123
7.5
55
−65
to 150
260 peak
1
Unit
°C
°C
°C/W
°C/W
°C/W
°C/W
°C
°C
−
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Internally limited by thermal shutdown, 150°C min.
2. 2 layer board, 1 in
2
Cu, 1 oz thickness.
3. 60−180 seconds minimum above 237°C.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
MAXIMUM RATINGS
Pin Symbol
V
CC
PGND
BST
Pin Name
Main Supply Voltage Input
Ground
Bootstrap Supply Voltage Input
V
MAX
15 V
0V
35 V wrt/PGND
40 V
v
50 ns wrt/PGND
15 V wrt/SW
35 V DC
40 V < 50 ns
BST + 0.3 V
35 V
v
50 ns wrt/PGND
15 V wrt/SW
V
CC
+ 0.3 V
6.5 V
6.5 V
V
MIN
−0.3
V
0V
−0.3
V wrt/SW
SW
DRVH
Switching Node
(Bootstrap Supply Return)
High−Side Driver Output
−5.0
V DC
−10
V < 200 ns
−0.3
V wrt/SW
−2.0
V < 200 ns wrt/SW
−0.3
V DC
−5.0
V < 200 ns
−0.3
V
−0.3
V
DRVL
IN
OD
NOTE:
Low−Side Driver Output
DRVH and DRVL Control Input
Output Disable
All voltages are with respect to PGND except where noted.
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3
NCP3420
ELECTRICAL CHARACTERISTICS
(Note 4) (V
CC
= 12 V, T
A
= 0°C to +85°C, T
J
= 0°C to +125°C unless otherwise noted.)
Characteristic
Supply
Supply Voltage Range
Supply Current
OD Input
Input Voltage High
Input Voltage Low
Hysteresis
Input Current
Propagation Delay Time
PWM Input
Input Voltage High
Input Voltage Low
Hysteresis
Input Current
High−Side Driver
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
SW Pulldown Resitance
Output Resistance, Unbiased
Transition Times
Propagation Delay (Note 5)
Low−Side Driver
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Output Resistance, Unbiased
Timeout Delay
Transition Times
Propagation Delay (Note 5)
Undervoltage Lockout
UVLO Startup
UVLO Shutdown
Hysteresis
Thermal Shutdown
Over Temperature Protection
Hysteresis
−
(Note 6)
(Note 6)
150
−
170
20
−
−
°C
°C
−
−
−
−
−
−
3.9
3.7
0.1
4.3
4.1
0.2
4.5
4.3
0.4
V
V
V
−
−
−
−
t
rDRVL
t
fDRVL
t
pdhDRVL
t
pdlDRVL
V
CC
= 12 V (Note 6)
V
CC
−
PGND = 12 V (Note 6)
V
CC
= PGND
DRVH−SW = 0
V
BST
−
V
SW
= 12 V, C
LOAD
= 3.0 nF
(See Figure 3)
V
BST
−
V
SW
= 12 V, C
LOAD
= 3.0 nF
(Note 6, t
pdhDRVL
Only) (See Figure 3)
−
−
10
−
−
−
15
10
1.8
1.0
−
85
16
11
30
30
3.0
2.5
55
−
30
25
45
45
W
W
kW
ns
ns
ns
ns
ns
−
−
−
−
t
rDRVH
t
fDRVH
t
pdhDRVH
t
pdlDRVH
V
BST
−
V
SW
= 12 V (Note 6)
V
BST
−
V
SW
= 12 V (Note 6)
SW to PGND
BST−SW = 0 V
V
BST
−
V
SW
= 12 V, C
LOAD
= 3.0 nF
(See Figure 3)
V
BST
−
V
SW
= 12 V, C
LOAD
= 3.0 nF
(See Figure 3)
−
−
10
10
−
−
20
10
1.8
1.0
−
−
16
11
30
30
3.0
2.5
55
55
30
25
45
45
W
W
kW
kW
ns
ns
ns
ns
V
PWM_HI
V
PWM_LO
−
−
−
−
−
No internal pull−up or pull−down resistors
2.0
−
−
−1.0
−
−
500
−
−
0.8
−
+1.0
V
V
mV
mA
V
OD_HI
V
OD_LO
−
−
t
pdlOD
t
pdhOD
−
−
−
No internal pull−up or pull−down resistors
−
2.0
−
−
−1.0
1.0
1.0
−
−
400
−
25
25
−
0.8
−
+1.0
45
45
V
V
mV
mA
ns
ns
V
CC
I
SYS
−
BST = 12 V, IN = 0 V
4.6
−
−
0.7
13.2
6.0
V
mA
Symbol
Condition
Min
Typ
Max
Unit
4. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
5. For propagation delays, “t
pdh
’’ refers to the specified signal going high; “t
pdl
’’ refers to it going low.
6. GBD: Guaranteed by design; not tested in production.
Specifications subject to change without notice.
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4
NCP3420
OD
V
OD_LO
t
pdlOD
90%
DRVH
or
DRVL
10%
t
pdhOD
V
OD_HI
Figure 2. Output Disable Timing Diagram
V
PWM_HI
IN
V
PWM_LO
t
pdlDRVL
t
fDRVL
90%
10%
t
pdhDRVH
DRVH−SW
10%
2V
10%
t
pdhDRVL
SW
t
rDRVH
90%
t
pdlDRVH
90%
t
fDRVH
10%
t
rDRVL
DRVL
90%
2V
Figure 3. Nonoverlap Timing Diagram
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