AT71201M
16M-Pixel Sensor
Datasheet
1. Features
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Full-frame Image Sensor 4096 × 4096 Pixels
11 µm × 11 µm Photo-MOS Pixel with 100% Aperture
Image Area: 45 × 45 mm
2
Frame Readout Through One, Two or Four Outputs
Data Rates Up to 4 × 40 MHz (Compatibility with 7.4 Frames per Second)
True 12-bit High Dynamic Range
Very Low Readout Noise
Very Low Dark Current (MPP Mode)
Optimized Resolution and Responsivity in the 400 to 1100 nm Spectrum
On-chip Thermometer for Each Image Zone
Additional Full-Frame Operating Modes:
– 4/3 Aspect Ratio: 4096 × 3072
– 2/1 Aspect Ratio: 4096 × 2048
– Binning 2 × 2 Pixels (Format 2048 × 2048 Pixels of 22 × 22 µm
2
)
– Binning 4 × 4 Pixels (Format 1024 × 1024 Pixels of 44 × 44 µm
2
)
2. Applications
Flexibility and performance make this device suitable for digital photography, graphic arts, medical or industrial applications
and scientific analysis.
3. Description
e2v’s AT71201M is a full-frame sensor based on charge-coupled device (CCD) technology. It can be used in a wide range
of applications thanks to operating mode flexibility, very high definition and high dynamic range.
The nominal photosensitive area comprises 4096 × 4096 useful pixels and is split into four independent zones that are
driven separately by four independent four-phase clock sets. Thus the sensor can be used in 12 main modes.
The large format and high definition make the device suitable for any application requiring precision.
The high sensitivity of the 11 × 11 µm
2
pixels with 100% fill factor provides a large bandwidth response up to 1100 nm
wavelength.
Two serial registers and four independent output amplifiers offer high-frequency functionality of 4 × 40 Msps or 7.4 frames
per second with high signal-to-noise ratio.
On customer request, frame transfer architecture:
– 2048 active lines, one memory zone with frame readout through one or two outputs.
– 2048 active lines, two memory zones with frame readout through two or four outputs.
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for the latest version of the datasheet
0900E–IMAGE–11/08
e2v semiconductors SAS 2008
AT71201M
Table 4-1.
Signal Name
PHILA [1;8]
PHILB [1;8]
PHILS [1;4]
PHIR [1;4]
PHIPA [1;4]
PHIPB [1;4]
PHIPC [1;4]
PHIPD [1;4]
PHITA
PHITB
PHIFCA
PHIFCB
VGS [1;4]
PIFCBNC
VOS [1;4]
VDD [1;4]
VS [1;4]
VDR [1;4]
VDE (2)
VDEA
VDEB
VTHL [1;4]
VTHH [1;4]
VSS (12)
Pin Description
Parameter
Register A clocks
Register B clocks
Summing clocks
Reset gates
Image zone A clocks
Image zone B clocks
Image zone C clocks
Image zone D clocks
Image zone to register A transfer clock
Image zone to register B transfert clock
Not used
Not used
Register output gate biases
Connect to ground
Video outputs
Amplifier drains
Amplifier sources
Reset drains
Peripheral lateral drain
Peripheral drain along register A
Peripheral drain along register B
Thermometer low 1 to 4
Thermometer high 1 to 4
Ground connection
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AT71201M
5. Block Diagram
Figure 5-1.
AT71201M Block Diagram Top View
ΦLs1
VGS1
ΦR1
VDR1
VS1
VOS1
VDD1
VTHH1
VTHL1
16 Prescans
VDEA
ΦLA1
to 4
ΦLA5
to 8
ΦTA
VS2
VOS2
VDD2
VTHH2
VTHL2
Φ
Ls2
VGS2
Φ
R2
VDR2
ΦTA
ΦPAj
24 vertical
references
ΦPAj
ΦPBj
VDE
4096 x 4096 useful pixels
(11 x 11 µm²) = 45 x 45 mm²
ΦPBj
VDE
ΦPCj
8 vertical and horizontal insulating
elements (including 4 dark ones)
ΦPCj
ΦPDj
ΦPDj
}
}
}
}
A Zone
B Zone
C Zone
D Zone
ΦTB
Φ
Ls3
VGS3
Φ
R3
VDR3
VS3
VOS3
VDD3
VTHH3
VTHL3
ΦLB1
to 4
VDEB
ΦLB5
to 8
VS4
Thermometer
Φ
Ls4
VOS4 VGS4
VDD4
Φ
R4
VTHH4 VDR4
VTHL4
ΦTB
Readout
modes
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AT71201M
6. Architectural Overview
6.1
General Parameters
Table 6-1.
Parameter
Pixel size
Number of useful pixels per line
Number of useful lines
Number of extra lines
Number of readout registers
Number of prescan CCD stages (per output)
Number of dark references (cells per line)
Number of outputs (2 per register)
MPP mode/low dark current mode
Anti-blooming functionality
Binning (summation) mode
Pixel clocking mode
Readout Register clocking mode
Specific function
Notes:
General Parameters
Value
11 × 11 µm²
4096
4096
8 per register
2
16
24
4
(1)
Yes (image zone)
no
Yes
(2)
4-phase
2-phase
Thermometer
1. The full-frame version can be read through one, two or four outputs.
2. Summation of lines into the register is made by a specific timing diagram. Integration time should be
adapted to prevent charge overflow.
A specific clock allows the column summation.
The pixel size is 11 × 11µm
2
with 100% fill factor (photo-MOS technology).
The sensor is compatible with a 180° rotation.
Image zone commands are split in four horizontal areas. Combination of
ΦPij
clocks allows various
transfer configurations.
Serial registers are driven by 8
ΦLi
clocks. An adapted combination of these allows transfer of 100% of
stages to the right or left side or 50% in each direction.
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