M4A3-128/64-10CANI datasheet, PDF

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M4A3-128/64-10CANI: DescriptionEE PLD, 10ns, CMOS, PBGA100, CABGA-100; CategoryProgrammable logic devices Programmable logic; File Size743KB，62 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com; Environmental Compliance

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M4A3-128/64-10CANI Overview

EE PLD, 10ns, CMOS, PBGA100, CABGA-100

M4A3-128/64-10CANI Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Lattice
Parts packaging code	BGA
package instruction	CABGA-100
Contacts	100
Reach Compliance Code	unknown
ECCN code	EAR99
maximum clock frequency	62.5 MHz
JESD-30 code	S-PBGA-B100
JESD-609 code	e1
length	10 mm
Humidity sensitivity level	3
Dedicated input times	2
Number of I/O lines	64
Number of terminals	100
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2 DEDICATED INPUTS, 64 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	LFBGA
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
Programmable logic type	EE PLD
propagation delay	10 ns
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	10 mm

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High Performance E

CMOS

In-System Programmable Logic

FEATURES

◆

High-performance, E

CMOS 3.3-V & 5-V CPLD families

◆

Flexible architecture for rapid logic designs

ispMACH

™

4A CPLD Family

◆

— Excellent First-Time-Fit

and reﬁt feature

— SpeedLocking

performance for guaranteed ﬁxed timing

— Central, input and output switch matrices for 100% routability and 100% pin-out retention

High speed

— 5.0ns t

Commercial and 7.5ns t

Industrial

— 182MHz f

CNT

32 to 512 macrocells; 32 to 768 registers

44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages

Flexible architecture for a wide range of design styles

— D/T registers and latches

— Synchronous or asynchronous mode

— Dedicated input registers

— Programmable polarity

— Reset/ preset swapping

Advanced capabilities for easy system integration

— 3.3-V & 5-V JEDEC-compliant operations

— JTAG (IEEE 1149.1) compliant for boundary scan testing

— 3.3-V & 5-V JTAG in-system programming

— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)

— Safe for mixed supply voltage system designs

— Programmable pull-up or Bus-Friendly

inputs and I/Os

— Hot-socketing

— Programmable security bit

— Individual output slew rate control

Advanced E

CMOS process provides high-performance, cost-effective solutions

Publication#

ISPM4A

Amendment/0

Rev:

Issue Date:

February 2003

M4A3-128/64-10CANI Related Products

	M4A3-128/64-10CANI	M4A3-128/64-12YNI	M4A3-128/64-55FANC	M4A3-128/64-12CANI	M4A3-128/64-7CANC	M4A3-128/64-12VC
Description	EE PLD, 10ns, CMOS, PBGA100, CABGA-100	EE PLD, 12ns, CMOS, PQFP100, PLASTIC, QFP-100	EE PLD, 5.5ns, CMOS, PBGA100, 0.80 MM PITCH, FBGA-100	EE PLD, 12ns, CMOS, PBGA100, CABGA-100	EE PLD, 7.5ns, CMOS, PBGA100, CABGA-100	EE PLD, 12ns, 128-Cell, CMOS, PQFP100, TQFP-100
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free	Contains lead
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	incompatible
package instruction	CABGA-100	QFP,	LFBGA,	CABGA-100	CABGA-100	TQFP-100
Reach Compliance Code	unknown	compliant	compliant	unknown	unknown	not_compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
maximum clock frequency	62.5 MHz	52.6 MHz	105 MHz	52.6 MHz	76.9 MHz	52.6 MHz
JESD-30 code	S-PBGA-B100	R-PQFP-G100	S-PBGA-B100	S-PBGA-B100	S-PBGA-B100	S-PQFP-G100
JESD-609 code	e1	e3	e1	e1	e1	e0
length	10 mm	20 mm	10 mm	10 mm	10 mm	14 mm
Humidity sensitivity level	3	3	3	3	3	3
Dedicated input times	2	2	-	2	2	2
Number of I/O lines	64	64	64	64	64	64
Number of terminals	100	100	100	100	100	100
Maximum operating temperature	85 °C	85 °C	70 °C	85 °C	70 °C	70 °C
organize	2 DEDICATED INPUTS, 64 I/O	2 DEDICATED INPUTS, 64 I/O	0 DEDICATED INPUTS, 64 I/O	2 DEDICATED INPUTS, 64 I/O	2 DEDICATED INPUTS, 64 I/O	2 DEDICATED INPUTS, 64 I/O
Output function	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFBGA	QFP	LFBGA	LFBGA	LFBGA	LFQFP
Package shape	SQUARE	RECTANGULAR	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH	FLATPACK	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260	245	260	260	260	240
Programmable logic type	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD
propagation delay	10 ns	12 ns	5.5 ns	12 ns	7.5 ns	12 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.5 mm	3.4 mm	1.5 mm	1.5 mm	1.5 mm	1.6 mm
Maximum supply voltage	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage	3 V	3 V	3 V	3 V	3 V	3 V
Nominal supply voltage	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)	Matte Tin (Sn)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Lead (Sn/Pb)
Terminal form	BALL	GULL WING	BALL	BALL	BALL	GULL WING
Terminal pitch	0.8 mm	0.65 mm	0.8 mm	0.8 mm	0.8 mm	0.5 mm
Terminal location	BOTTOM	QUAD	BOTTOM	BOTTOM	BOTTOM	QUAD
Maximum time at peak reflow temperature	40	40	40	40	40	30
width	10 mm	14 mm	10 mm	10 mm	10 mm	14 mm
Maker	Lattice	Lattice	-	Lattice	Lattice	Lattice
Parts packaging code	BGA	QFP	BGA	BGA	BGA	-
Contacts	100	100	100	100	100	-

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