GS8324Z36B-133IT datasheet, PDF

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GS8324Z36B-133IT: DescriptionZBT SRAM, 1MX36, 10ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119; Categorystorage storage; File Size1MB，46 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

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GS8324Z36B-133IT Overview

ZBT SRAM, 1MX36, 10ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119

GS8324Z36B-133IT Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	GSI Technology
Parts packaging code	BGA
package instruction	BGA,
Contacts	119
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	10 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE; IT CAN ALSO OPERATE WITH 3.3V SUPPLY
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	37748736 bit
Memory IC Type	ZBT SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	119
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	1MX36
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.99 mm
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

119- and 209-Pin BGA

Commercial Temp

Industrial Temp

Features

• NBT (No Bus Turn Around) functionality allows zero wait

Read-Write-Read bus utilization; fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

• FT pin for user-configurable flow through or pipeline operation

• IEEE 1149.1 JTAG-compatible Boundary Scan

• ZQ mode pin for user-selectable high/low output drive

• 2.5 V or 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119- and 209-bump BGA package

Pipeline

3-1-1-1

3.3 V

tCycle

Curr (x18)

Curr (x36)

Curr (x72)

Curr (x18)

Curr (x36)

Curr (x72)

tCycle

Curr (x18)

Curr (x36)

Curr (x72)

Curr (x18)

Curr (x36)

Curr (x72)

-250 -225 -200 -166 -150 -133 Unit

2.3 2.5 3.0 3.5 3.8 4.0 ns

4.0 4.4 5.0 6.0 6.6 7.5 ns

365

560

660

360

550

640

6.0

7.0

235

300

350

235

300

340

335

510

600

330

500

590

6.5

7.5

230

300

350

230

300

340

305

460

540

305

460

530

7.5

8.5

210

270

300

210

270

300

265

400

460

260

390

450

8.5

200

270

300

200

270

300

245

370

430

240

360

420

195

270

300

195

270

300

215

330

380

215

330

370

150

200

220

145

190

220

2M x 18, 1M x 36, 512K x 72

36Mb Sync NBT SRAMs

250 MHz–133MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

ADV. The burst address counter may be configured to count in

either linear or interleave order with the Linear Burst Order (LBO)

input. The Burst function need not be used. New addresses can be

loaded on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the

user via the FT mode . Holding the FT mode pin low places the

RAM in Flow Through mode, causing output data to bypass the

Data Output Register. Holding FT high places the RAM in

Pipeline mode, activating the rising-edge-triggered Data Output

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write control

inputs.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ low)

for multi-drop bus applications and normal drive strength (ZQ

floating or high) point-to-point applications. See the Output Driver

Characteristics chart for details.

2.5 V

Flow

Through

2-1-1-1

3.3 V

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High)

of the ZZ signal, or by stopping the clock (CK). Memory data is

retained during Sleep mode.

Core and Interface Voltages

The GS8324Z18/36/72 operates on a 2.5 V or 3.3 V power supply.

All input are 3.3 V and 2.5 V compatible. Separate output power

DDQ

) pins are used to decouple output noise from the internal

circuits and are 3.3 V and 2.5 V compatible.

2.5 V

Functional Description

Applications

The GS8324Z18/36/72 is a 37,748,736-bit high performance 2-die

synchronous SRAM module with a 2-bit burst address counter.

Although of a type originally developed for Level 2 Cache

applications supporting high performance CPUs, the device now

finds application in synchronous SRAM applications, ranging

from DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated

Rev: 1.00 10/2001

1/46

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

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