DM5450J datasheet, PDF - EEWORLD Datasheet

DM5450J: DescriptionIC,LOGIC GATE,2 2/2-IN AND-NOR,STD-TTL,DIP,14PIN,CERAMIC; Categorylogic logic; File Size70KB，3 Pages; ManufacturerNational Semiconductor（TI ）; Websitehttp://www.ti.com

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DM5450J Overview

IC,LOGIC GATE,2 2/2-IN AND-NOR,STD-TTL,DIP,14PIN,CERAMIC

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	National Semiconductor（TI ）
package instruction	DIP, DIP14,.3
Reach Compliance Code	unknown
JESD-30 code	R-XDIP-T14
JESD-609 code	e0
Logic integrated circuit type	AND-OR-INVERT GATE
MaximumI(ol)	0.016 A
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
power supply	5 V
Maximum supply current (ICC)	14 mA
Prop。Delay @ Nom-Sup	30 ns
Certification status	Not Qualified
Schmitt trigger	NO
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL

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