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SN74LVC1G10DBVRE4

Description
Logic Gates Sgl 3-Inp Pos-NAND Gate
Categorylogic    logic   
File Size669KB,15 Pages
ManufacturerTexas Instruments
Websitehttp://www.ti.com.cn/
Environmental Compliance
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SN74LVC1G10DBVRE4 Overview

Logic Gates Sgl 3-Inp Pos-NAND Gate

SN74LVC1G10DBVRE4 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerTexas Instruments
Parts packaging codeSOT-23
package instructionLSSOP, TSOP6,.11,37
Contacts6
Reach Compliance Codeunknow
seriesLVC/LCX/Z
JESD-30 codeR-PDSO-G6
JESD-609 codee4
length2.9 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeNAND GATE
MaximumI(ol)0.024 A
Humidity sensitivity level1
Number of functions1
Number of entries3
Number of terminals6
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLSSOP
Encapsulate equivalent codeTSOP6,.11,37
Package shapeRECTANGULAR
Package formSMALL OUTLINE, LOW PROFILE, SHRINK PITCH
method of packingTR
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Su5 ns
propagation delay (tpd)18 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height1.45 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)1.65 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch0.95 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width1.6 mm

SN74LVC1G10DBVRE4 Related Products

SN74LVC1G10DBVRE4 SN74LVC1G10DCKRE4
Description Logic Gates Sgl 3-Inp Pos-NAND Gate Logic Gates SNGL 3 Input Pos NAND Gate
Is it lead-free? Lead free Lead free
Is it Rohs certified? conform to conform to
Maker Texas Instruments Texas Instruments
Parts packaging code SOT-23 SOIC
package instruction LSSOP, TSOP6,.11,37 TSSOP, TSSOP6,.08
Contacts 6 6
Reach Compliance Code unknow unknow
series LVC/LCX/Z LVC/LCX/Z
JESD-30 code R-PDSO-G6 R-PDSO-G6
JESD-609 code e4 e4
length 2.9 mm 2 mm
Load capacitance (CL) 50 pF 50 pF
Logic integrated circuit type NAND GATE NAND GATE
MaximumI(ol) 0.024 A 0.024 A
Humidity sensitivity level 1 1
Number of functions 1 1
Number of entries 3 3
Number of terminals 6 6
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C
Output characteristics 3-STATE 3-STATE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code LSSOP TSSOP
Encapsulate equivalent code TSOP6,.11,37 TSSOP6,.08
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, LOW PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing TR TR
Peak Reflow Temperature (Celsius) 260 260
power supply 3.3 V 3.3 V
Prop。Delay @ Nom-Su 5 ns 5 ns
propagation delay (tpd) 18 ns 18 ns
Certification status Not Qualified Not Qualified
Schmitt trigger NO NO
Maximum seat height 1.45 mm 1.1 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V
Minimum supply voltage (Vsup) 1.65 V 1.65 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V
surface mount YES YES
technology CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL
Terminal surface Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form GULL WING GULL WING
Terminal pitch 0.95 mm 0.65 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED
width 1.6 mm 1.25 mm

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