PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8427-02
700MH
Z
, L
OW
J
ITTER
LVCMOS/C
RYSTAL
-
TO
-LVHSTL F
REQUENCY
S
YNTHESIZER
F
EATURES
•
6 differential LVHSTL outputs
•
Selectable crystal input interface or TEST_CLK input
•
TEST_CLK accepts the following input types:
LVCMOS, LVTTL
•
Output frequency range: 15.625MHz to 700MHz
•
VCO range: 250MHz to 700MHz
•
Serial interface for programming feedback and output dividers
•
Supports SSC, -0.5% downspread. Can be enabled through
use of the serial programming interface.
•
Output skew: 60ps (typical)
•
Cycle-to-cycle jitter: 30ps (typical)
•
2.5V core/1.8V output supply voltage
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
G
ENERAL
D
ESCRIPTION
The ICS8427-02 is a general purpose, six
LVHSTL output high frequency synthesizer and
HiPerClockS™
a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8427-02 can support a very wide output fre-
quency range of 15.625MHz to 700MHz. The device powers
up at a default output frequency of 200MHz with a 16.66MHz
crystal interface, and the frequency can then be changed
using the serial programming interface to change the M feed-
back divider and N output divider. Frequency steps as small
as 125KHz can be achieved using a 16.66MHz crystal and
the output divider set for
÷16.
The low jitter and frequency
range of the ICS8427-02 make it an ideal clock generator for
most clock tree applications.
ICS
B
LOCK
D
IAGRAM
VCO_SEL
XTAL_SEL
TEST_CLK
XTAL_IN
OSC
XTAL_OUT
÷
16
1
0
P
IN
A
SSIGNMENT
VCO_SEL
XTAL_IN
nFOUT0
nFOUT1
FOUT0
FOUT1
V
DDO
V
DD
32 31 30 29 28 27 26 25
V
DDO
FOUT2
nFOUT2
V
DDO
FOUT3
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
TEST
V
DD
FOUT4
nFOUT4
V
DDO
FOUT5
nFOUT5
GND
24
23
22
XTAL_OUT
TEST_CLK
XTAL_SEL
V
DDA
S_LOAD
S_DATA
S_CLOCK
MR
ICS8427-02
21
20
19
18
17
PLL
PHASE DETECTOR
VCO
÷
M
÷
2
0
1
nFOUT3
÷
1,
÷
2,
÷
4,
÷
8,
÷
16
OE
GND
FOUT0
nFOUT0
FOUT1
nFOUT1
FOUT2
nFOUT2
FOUT3
nFOUT3
FOUT4
nFOUT4
FOUT5
nFOUT5
MR
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
OE
S_LOAD
S_DATA
S_CLOCK
CONFIGURATION
INTERFACE
LOGIC
TEST
32-Lead VFQFN
5mm x 5mm x 0.75mm package body
K Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8427BY-02
www.icst.com/products/hiperclocks.html
REV. A MARCH 4, 2005
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8427-02
700MH
Z
, L
OW
J
ITTER
LVCMOS/C
RYSTAL
-
TO
-LVHSTL F
REQUENCY
S
YNTHESIZER
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 16MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 6 NOTE 1.
The ICS8427-02 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth.
A parallel-resonant, fundamental crystal is used as the input to
the on-chip oscillator. The output of the oscillator is divided by
16 prior to the phase detector. With a 16.66MHz crystal, this
provides a 1.0417MHz reference frequency. The VCO of the
PLL operates over a range of 250MHz to 700MHz. The output of
the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output fre-
quency to be 2M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL
output buffers. The divider provides a 50% output duty cycle.
The ICS8427-02 powers up by default to 200MHz output fre-
quency, using a 16.66MHz crystal (M = 192, N = 2). The out-
put frequency can be changed after power-up by using the
serial interface to program the M feedback divider and the N
output divider.
The relationship between the VCO frequency, the crystal fre-
quency and the M divider is defined as follows:
fxtal x 2M
fVCO =
16
The M value and the required values of M0 through M8 are shown
in Table 3B, Programmable VCO Frequency Function Table. Valid
M values for which the PLL will achieve lock for a 16.66MHz
reference are defined as 120
≤
M
≤
336. The frequency out is
defined as follows: fout = fVCO = fxtal x 2M
N
16
N
Serial operation occurs when S_LOAD is LOW. The shift
register is loaded by sampling the S_DATA bits with the rising
edge of S_CLOCK. The contents of the shift register are
loaded into the M divider and N output divider when S_LOAD
transitions from LOW-to-HIGH. The M divide and N output
divide values are latched on the HIGH-to-LOW transition of
S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input
is passed directly to the M divider and N outputdivider on each
rising edge of S_CLOCK. The serial mode can be used to
program the M and N bits and test bits T1 and T0. The internal
registers T0 and T1 determine the state of the TEST output
as follows:
T1
0
0
1
1
T0
0
1
(Power-up
Default)
0
1
TEST Output
LOW
S_Data, Shift Register Input
Output of M divider
CMOS Fout
S_CLOCK
S_DATA
t
S_LOAD
T1
S
T0
H
N2
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
SSC
t
t
S
F
IGURE
1. S
ERIAL
L
OAD
O
PERATIONS
NOTE: Default Output Frequency, using a 16.66MHz crystal
on power-up = 200MHz (M = 192, N = 2) SSC off
8427BY-02
www.icst.com/products/hiperclocks.html
2
REV. A MARCH 4, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8427-02
700MH
Z
, L
OW
J
ITTER
LVCMOS/C
RYSTAL
-
TO
-LVHSTL F
REQUENCY
S
YNTHESIZER
N D
IVIDERS
, SSC
AND
M
Test Mode
Control Register
AND
T
EST
M
ODE
C
ONTROL
B
ITS
SSC Control
Register
N Divider
M Divider
➤
T1
➤
➤
T0
N2
N1
➤
➤
N0
M8
M7
M6
M5
M4
M3
M2
M1
➤
➤
➤
M0
SSC
➤
➤
➤
➤
➤
➤
➤
➤
➤
➤
➤
➤
➤
➤
➤
➤
SSC
Data transfer from shift register
to M and N dividers and SSC and
Test Control Bits on a low-to-high
transition of S_LOAD.
S_DATA
➤
T1
T0
N2
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
Shift Register
TEST Output
T1:T0 = 01
8427-02 S
HIFT
R
EGISTER
O
PERATION
– R
EAD
B
ACK
C
APABILITY
1. Device powers up by default in Test Mode 01.
The Test Output in this case is wired to the shift register.
2. Shift in serial data stream and latch into M, N, T1, T0 and SSC Control Bits.
Shift in T1:T0=00, so that the TEST Output will be turned off after the bits are shifted in and latched.
TEST Output
T1
T0
N2
N1
N0
M8
M7
M6
M5
M4 M3
M2
M1
M0 SSC
S_CLOCK
S_DATA
t
T1
S
T0
N2
N1
N0
M8
M7
M6
M5
M4 M3
M2
M1
M0 SSC
t
S_LOAD
H
t
S
Data transferred to M, N dividers, TEST and SSC Control Bits.
Changes to M, N, SSC and TEST mode bits take affect at this time.
Data latched into M, N Dividers, TEST and SSC control bits.
8427BY-02
www.icst.com/products/hiperclocks.html
3
REV. A MARCH 4, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8427-02
700MH
Z
, L
OW
J
ITTER
LVCMOS/C
RYSTAL
-
TO
-LVHSTL F
REQUENCY
S
YNTHESIZER
Type
Power
Output
Output
Input
Power
Output
Power
Output
Output
Pullup
Description
Output supply pins.
Differential output for the synthesizer. LVHSTL interface levels.
Differential output for the synthesizer. LVHSTL interface levels.
Active High output enable. When HIGH, the outputs are enabled.
When LOW, all 6 outputs drive differential low, FOUTx = Low,
nFOUTx = High. LVCMOS/LVTTL interface levels.
Power supply ground.
Test output which is ACTIVE in the serial mode of operation.
LVCMOS/LVTTL interface levels.
Core supply pin.
Differential output for the synthesizer. LVHSTL interface levels.
Differential output for the synthesizer. LVHSTL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs FOUTx to go low and the inver ted
Pulldown
outputs nFOUTx to go high. When logic LOW, the internal dividers
and the outputs are enabled. LVCMOS/LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
Pullup
on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of
Pullup
S_CLOCK. LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the dividers.
Pulldown
LVCMOS/LVTTL interface levels.
Analog supply pin.
Selects between XTAL input or test input as the PLL reference
source. Selects XTAL input when HIGH. Selects TEST_CLK
Pullup
when LOW. LVCMOS/LVTTL interface levels.
Pulldown Test clock input. LVCMOS/LVTTL interface levels.
Cr ystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Determines whether synthesizer is in PLL or bypass mode.
Pullup
LVCMOS/LVTTL interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 4, 13, 30
2, 3
5, 6
7
8, 16
9
10, 26
11, 12
14, 15
Name
V
DDO
FOUT2,
nFOUT2
FOUT3,
nFOUT3
OE
GND
TEST
V
DD
FOUT4,
nFOUT4
FOUT5,
nFOUT5
MR
17
Input
18
19
20
21
22
23
24, 25
27
28, 29
S_CLOCK
S_DATA
S_LOAD
V
DDA
XTAL_SEL
TEST_CLK
XTAL_OUT,
XTAL_IN
VCO_SEL
Input
Input
Input
Power
Input
Input
Input
Input
FOUT0,
Output
Differential output for the synthesizer. LVHSTL interface levels.
nFOUT0
FOUT1,
31, 32
Output
Differential output for the synthesizer. LVHSTL interface levels.
nFOUT1
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
8427BY-02
www.icst.com/products/hiperclocks.html
4
REV. A MARCH 4, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8427-02
700MH
Z
, L
OW
J
ITTER
LVCMOS/C
RYSTAL
-
TO
-LVHSTL F
REQUENCY
S
YNTHESIZER
Outputs
FOUT0:FOUT5
Disabled; LOW
Disabled; LOW
Enabled
nFOUT0:nFOUT5
Disabled; HIGH
Disabled; HIGH
Enabled
TEST_CLK
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
OE
0
0
1
XTAL_SEL
0
1
0
Selected Source
XTAL_IN, XTAL_OUT
TEST_CLK
1
1
XTAL_IN, XTAL_OUT
Enabled
Enabled
After OE switches, the clock outputs are disabled or enabled following a rising and falling VCO edge
as shown in
Figure 2.
nVCO
VCO
Disabled
Enabled
OE
nFOUT0:5
FOUT0:5
F
IGURE
2. OE T
IMING
D
IAGRAM
8427BY-02
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5
REV. A MARCH 4, 2005
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