24FC32
32K 5.0V 1 MHz CMOS Serial EEPROM
FEATURES
• Voltage operating range: 4.5V to 5.5V
- Maximum write current 3 mA at 5.5V
- Maximum read current 150
µA
at 5.5V
- Standby current 1
µA
typical
• 1 MHz SE2.bus two wire protocol
• Self-timed write cycle (including auto-erase)
• Power on/off data protection circuitry
• Endurance:
-
10,000,000 ERASE/WRITE cycles guaran-
teed for a 4K block
-
100,000 E/W cycles guaranteed for a 28K
block
• variable page size up to 64 bytes
• 8 byte x 8 line input cache (64 bytes)
for fast write loads
• Schmitt trigger inputs for noise suppression
• 2 ms typical write cycle time, byte or page
• Factory programming (QTP) available
• Up to 8 chips may be connected to the same bus
for up to 256K bits total memory
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP/SOIC packages
• Temperature ranges:
- Commercial: 0°C to +70°C
- Industrial: -40°C to +85°C
PACKAGE TYPE
PDIP
A0
A1
A2
V
SS
1
2
24FC32
3
4
6
5
SCL
SDA
8
7
V
CC
NC
SOIC
A0
A1
A2
V
SS
1
8
V
CC
NC
SCL
SDA
7
2
24FC32
6
3
4
5
BLOCK DIAGRAM
A0..A2
HV GENERATOR
DESCRIPTION
The Microchip Technology Inc. 24FC32 is a 4K x 8 (32K
bit) Serial Electrically Erasable PROM (EEPROM) with
a high-speed 1 MHz SE2.bus whose protocol is
functionally equivalent to the industry-standard I2C
bus. This device has been developed for advanced,
low
power applications such
as
personal
communications or data acquisition. The 24FC32
features an input cache for fast write loads with a
capacity of eight 8-byte pages, or 64 bytes. It also
features a fixed 4K-bit block of ultra-high endurance
memory for data that changes frequently. The 24FC32
is capable of both random and sequential reads up to
the 32K boundary. Functional address lines allow up to
8 - 24FC32 devices on the same bus, for up to 256K
bits address space. The 24FC32 is available in the
standard 8-pin plastic DIP and 8-pin surface mount
SOIC package.
I/O
CONTROL
LOGIC
I/O
SCL
SDA
MEMORY
CONTROL
LOGIC
XDEC
EEPROM
ARRAY
PAGE LATCHES
CACHE
YDEC
V
CC
V
SS
SENSE AMP
R/W CONTROL
I
2
C is a trademark of Philips Corporation
©
1995 Microchip Technology Inc.
DS21126A-page 1
24FC32
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name
A0..A2
V
SS
SDA
SCL
V
CC
NC
PIN FUNCTION TABLE
Function
User Configurable Chip Selects
Ground
Serial Address/Data I/O
Serial Clock
+4.5V to 5.5V Power Supply
No Internal Connection
V
CC
........................................................................7.0V
All inputs and outputs w.r.t. V
SS
.....-0.6V to V
CC
+1.0V
Storage temperature ..........................-65°C to +150°C
Ambient temp. with power applied .....-65°C to +125°C
Soldering temperature of leads (10 seconds) .. +300°C
ESD protection on all pins
..................................... ≥
4 kV
*Notice:
Stresses above those listed under “Maximum Ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
V
CC
= +4.5V to +5.5V
Commercial (C): Tamb = 0°C to +70°C
Industrial (I):
Tamb = -40°C to +85°C
Parameter
Symbol
Min
Max
Units
Conditions
A0, A1, A2, SCL and SDA pins:
High level input voltage
Low level input voltage
Hysteresis of SCL and SDA
Low level output voltage of SDA
Input leakage current
Output leakage current
Pin capacitance
(all inputs/outputs)
Operating current
Standby current
V
IH
V
IL
V
HYS
V
OL
I
LI
I
LO
C
INT
I
CC
W
RITE
I
CC
Read
I
CCS
0.7 Vcc
—
0.05 Vcc
—
-10
-10
—
—
—
—
—
0.3 Vcc
—
0.40
10
10
10
3
150
5
(1 typical)
V
V
V
V
µA
µA
pF
mA
µA
µA
Note 1
I
OL
= 3.0 mA
V
IN
= 0.1V
TO
V
CC
V
OUT
= 0.1V to V
CC
V
CC
= 5.0V (Note 1)
Tamb = 25°C, Fclk = 1 MHz
V
CC
= 5.5V, SCL = 1 MHz
V
CC
= 5.5V, SCL = 1 MHz
V
CC
= 5.5V,
SCL = SDA = V
CC
Note 1
Note 1: This parameter is periodically sampled and not 100% tested.
FIGURE 1-1:
BUS TIMING START/STOP
SCL
T
HD
:
STA
T
SU
:
STA
SDA
V
HYS
T
SU
:
STO
START
STOP
DS21126A-page 2
©
1995 Microchip Technology Inc.
24FC32
TABLE 1-3:
AC CHARACTERISTICS
1 MHz Bus
Parameter
Symbol
Min
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
START condition setup
time
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
Write cycle time
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
T
SU
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
T
WR
0
500
500
—
—
250
250
0
100
250
—
500
—
Max
1000
—
—
300
100
—
—
—
—
—
350
—
5
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 2
Time the bus must be free before a new transmis-
sion can start
Note 1
Note 1
After this period the first clock pulse is generated
Only relevant for repeated START condition
Units
Remarks
ms/page Note 3
Note 1: Not 100 percent tested.
Note 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 100 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
Note 3: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write
cache for total time.
FIGURE 1-2:
BUS TIMING DATA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
T
F
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
SCL
T
SU
:
STA
SDA
IN
SDA
OUT
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
T
LOW
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
T
HIGH
T
HD
:
DAT
T
HD
:
STA
T
SP
T
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA AA
AA
AA AA
AA AA
AA AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
T
SU
:
DAT
T
SU
:
STO
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
T
R
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
T
AA
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
T
BUF
©
1995 Microchip Technology Inc.
DS21126A-page 3
24FC32
2.0
FUNCTIONAL DESCRIPTION
3.4
Data Valid (D)
The 24FC32 supports a bidirectional two-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus must be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24FC32 works
as slave. Both master and slave can operate as
transmitter or receiver but the master device
determines which mode is activated.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.
3.0
BUS CHARACTERISTICS
The following
bus protocol
has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this acknowledge
bit.
Note:
The 24FC32 does not generate any
acknowledge
bits
if
an
internal
programming cycle is in progress.
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START
condition.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account.
During reads, a master must signal an end of data to
the slave by NOT generating an acknowledge bit on the
last byte that has been clocked out of the slave. In this
case, the slave (24FC32) will leave the data line HIGH
to enable the master to generate the STOP condition.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
FIGURE 3-1:
(A)
SCL
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B)
(D)
(D)
(C)
(A)
SDA
AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA
START
Condition
Address
Data Allowed
or
to Change
Acknowledge
Valid
STOP
Condition
DS21126A-page 4
©
1995 Microchip Technology Inc.
24FC32
4.0
4.1
BUS CHARACTERISTICS
Device Addressing and Operation
(Figure 4-1)
device outputs an acknowledge signal on the SDA line.
Depending on the state of the R/W bit, the 24FC32 will
select a read or write operation.
Operation
Read
Write
Control
Code
1010
1010
Device Select
Device Address
Device Address
R/W
1
0
A control byte is the first byte received following the
start condition from the master device. The control byte
consists of a four bit control code; for the 24FC32 this
is set as 1010 binary for read and write operations. The
next three bits of the control byte are the device select
bits (A2, A1, A0). They are used by the master device
to select which of the eight devices are to be accessed.
These bits are in effect the three most significant bits of
the word address. The last bit of the control byte (R/W)
defines the operation to be performed. When set to a
one a read operation is selected, and when set to a
zero a write operation is selected. The next two bytes
received define the address of the first data byte
(Figure 4-2). Because only A11..A0 are used, the upper
four address bits must be zeros. The most significant
bit of the most significant byte of the address is
transferred first. Following the start condition, the
24FC32 monitors the SDA bus checking the device
type identifier being transmitted. Upon receiving a 1010
code and appropriate device select bits, the slave
FIGURE 4-1:
CONTROL BYTE
ALLOCATION
READ/WRITE
SLAVE ADDRESS
R/W
A
START
1
X = don’t care
0
1
0
A2
A1
A0
FIGURE 4-2:
ADDRESS SEQUENCE BIT ASSIGNMENTS
CONTROL
BYTE
ADDRESS
BYTE 1
ADDRESS
BYTE 0
1
0
1
0
A A
2 1
A
0
R
/W
0
0
0
A A A
0 11 10 9
A
8
A
7
•
•
•
•
•
•
A
0
Slave
Address
Device
Select
Bits
©
1995 Microchip Technology Inc.
DS21126A-page 5