NDF04N62Z, NDD04N62Z
N-Channel Power MOSFET
620 V, 2.0
W
Features
•
•
•
•
•
Low ON Resistance
Low Gate Charge
ESD Diode−Protected Gate
100% Avalanche Tested
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
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V
DSS
620 V
R
DS(ON)
(MAX) @ 2 A
2.0
W
ABSOLUTE MAXIMUM RATINGS
(T
C
= 25°C unless otherwise noted)
Parameter
Drain−to−Source Voltage
Continuous Drain Current R
qJC
Continuous Drain Current R
qJC
, T
A
=
100°C
Pulsed Drain Current,
V
GS
@ 10V
Power Dissipation R
qJC
(Note 1)
Gate−to−Source Voltage
Single Pulse Avalanche Energy,
I
D
= 4.0 A
ESD (HBM) (JESD22−A114)
RMS Isolation Voltage
(t = 0.3 sec., R.H.
≤
30%, T
A
=
25°C) (Figure 14)
Peak Diode Recovery
Continuous Source Current
(Body Diode)
Maximum Temperature for Soldering
Leads, 0.063″
(1.6 mm) from Case for 10 s
Package Body for 10 s
Operating Junction and
Storage Temperature Range
Symbol
V
DSS
I
D
I
D
I
DM
P
D
V
GS
E
AS
V
esd
V
ISO
NDF
620
4.4
(Note 2)
2.8
(Note 2)
18
(Note 2)
28
±30
120
3000
4500
−
4.1
2.6
16
83
NDD
Unit
V
A
A
A
W
V
mJ
V
V
1
dv/dt
I
S
T
L
4.5 (Note 3)
4.0
300
260
V/ns
A
°C
1
3
NDD04N62Z−1G
IPAK
CASE 369D
2
1 2
3
2
4
S (3)
N−Channel
D (2)
G (1)
4
T
PKG
3
NDF04N62ZG
TO−220FP
CASE 221D
NDD04N62ZT4G
DPAK
CASE 369AA
T
J
, T
stg
−55
to 150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface mounted on FR4 board using 1″ sq. pad size (Cu area = 1.127 in sq
[2 oz] including traces).
2. Limited by maximum junction temperature
3. I
SD
= 4.0 A, di/dt
≤
100 A/ms, V
DD
≤
BV
DSS
, T
J
= +150°C
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
This document contains information on some products that are still under development.
ON Semiconductor reserves the right to change or discontinue these products without
notice.
©
Semiconductor Components Industries, LLC, 2011
September, 2011
−
Rev. 2
1
Publication Order Number:
NDF04N62Z/D
NDF04N62Z, NDD04N62Z
THERMAL RESISTANCE
Parameter
Junction−to−Case (Drain)
Junction−to−Ambient Steady State
NDF04N62Z
NDD04N62Z
(Note 4) NDF04N62Z
(Note 1) NDD04N62Z
(Note 4) NDD04N62Z−1
Symbol
R
qJC
R
qJA
Value
4.4
1.5
50
38
80
Unit
°C/W
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Drain−to−Source Leakage Current
V
GS
= 0 V, I
D
= 1 mA
Reference to 25°C,
I
D
= 1 mA
V
DS
= 620 V, V
GS
= 0 V
V
GS
=
±20
V
V
GS
= 10 V, I
D
= 2.0 A
V
DS
= V
GS
, I
D
= 50
mA
V
DS
= 15 V, I
D
= 2.0 A
25°C
125°C
I
GSS
R
DS(on)
V
GS(th)
g
FS
C
iss
C
oss
C
rss
Q
g
V
DD
= 310 V, I
D
= 4.0 A,
V
GS
= 10 V
Q
gs
Q
gd
V
GP
R
g
t
d(on)
V
DD
= 310 V, I
D
= 4.0 A,
V
GS
= 10 V, R
G
= 5
Ω
t
r
t
d(off)
t
f
3.0
3.3
535
62
14
19
3.9
10
6.4
4.7
12
13
25
14
V
W
ns
nC
1.8
BV
DSS
DBV
DSS
/
DT
J
I
DSS
620
0.6
1
50
±10
2.0
4.5
mA
W
V
S
pF
V
V/°C
mA
Test Conditions
Symbol
Min
Typ
Max
Unit
Gate−to−Source Forward Leakage
ON CHARACTERISTICS
(Note 5)
Static Drain−to−Source
On−Resistance
Gate Threshold Voltage
Forward Transconductance
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Gate−to−Source Charge
Gate−to−Drain (“Miller”) Charge
Plateau Voltage
Gate Resistance
RESISTIVE SWITCHING CHARACTERISTICS
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
V
DS
= 25 V, V
GS
= 0 V,
f = 1.0 MHz
SOURCE−DRAIN DIODE CHARACTERISTICS
(T
C
= 25°C unless otherwise noted)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
4. Insertion mounted
5. Pulse Width
≤
380
ms,
Duty Cycle
≤
2%.
I
S
= 4.0 A, V
GS
= 0 V
V
GS
= 0 V, V
DD
= 30 V
I
S
= 4.0 A, di/dt = 100 A/ms
V
SD
t
rr
Q
rr
285
1.3
1.6
V
ns
mC
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2
NDF04N62Z, NDD04N62Z
TYPICAL CHARACTERISTICS
8
T
J
= 25°C
I
D
, DRAIN CURRENT (A)
6
8
10 V
7V
6.8 V
6.6 V
4
6.4 V
6.2 V
2
6.0 V
5.8 V
0
5.6 V
0
5
10
15
20
25
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
0
T
J
=
−55°C
3
4
5
6
7
8
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
V
DS
≥
30 V
I
D
, DRAIN CURRENT (A)
6
15 V
4
T
J
= 150°C
2
T
J
= 25°C
Figure 1. On−Region Characteristics
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE (W)
3.5
3
2.5
2
1.5
1
I
D
= 2 A
T
J
= 25°C
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE (W)
3
Figure 2. Transfer Characteristics
T
J
= 25°C
2.5
2
V
GS
= 10 V
1.5
5
6
7
V
GS
(V)
8
9
10
1
0.5
1
1.5
2
2.5
3
3.5
4
I
D
, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate Voltage
2.6
R
DS(on)
, DRAIN−TO−SOURCE RES-
ISTANCE (NORMALIZED)
BVDSS, NORMALIZED BREAK-
DOWN VOLTAGE (V)
I
D
= 2 A
V
GS
= 10 V
2
1.15
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
I
D
= 1 mA
1.1
1.05
1.0
0.95
0.9
−50
1.4
0.8
0.2
−50
−25
0
25
50
75
100
125
150
−25
0
25
50
75
100
125
150
T
J
, JUNCTION TEMPERATURE (°C)
T
J
, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. BVDSS Variation with Temperature
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3
NDF04N62Z, NDD04N62Z
TYPICAL CHARACTERISTICS
10,000
V
GS
= 0 V
1000
C, CAPACITANCE (pF)
I
DSS
, LEAKAGE (nA)
T
J
= 150°C
1000
800
600
400
C
oss
200
10
0
C
rss
0
50
100
150
200
C
iss
1200
V
GS
= 0 V
T
J
= 25°C
100
T
J
= 100°C
0
100
200
300
400
500
600
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Drain−to−Source Leakage Current
vs. Voltage
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
20
400
1000
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 8. Capacitance Variation
15
V
DS
Qgs
5
QT
300
V
DD
= 310 V
I
D
= 4 A
V
GS
= 10 V
t, TIME (ns)
100
t
d(off)
t
r
t
f
t
d(on)
10
10
Qgd
V
GS
V
DS
= 310 V
T
J
= 25°C
I
D
= 4 A
0
2
4
6
8
10
12
14
16
18
Qg, TOTAL GATE CHARGE (nC)
200
100
0
0
20
1
1
10
R
G
, GATE RESISTANCE (W)
100
Figure 9. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
4
I
S
, SOURCE CURRENT (A)
V
GS
= 0 V
T
J
= 25°C
3
100
Figure 10. Resistive Switching Time Variation
vs. Gate Resistance
I
D
, DRAIN CURRENT (A)
10
dc
1
10 ms
1 ms
100
ms
10
ms
2
1
0.1
V
GS
≤
30 V
Single Pulse
T
C
= 25°C
R
DS(on)
Limit
Thermal Limit
Package Limit
1
10
100
1000
0
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.01
V
SD
, SOURCE−TO−DRAIN VOLTAGE (V)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Diode Forward Voltage vs. Current
Figure 12. Maximum Rated Forward Biased
Safe Operating Area for NDF04N62Z
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4
NDF04N62Z, NDD04N62Z
TYPICAL CHARACTERISTICS
10
1.0
R(t) (C/W)
50% (DUTY CYCLE)
20%
10%
5.0%
2.0%
1.0%
SINGLE PULSE
R
qJC
= 4.4°C/W
Steady State
0.1
0.01
0.001
0.000001
0.00001
0.0001
0.001
0.01
PULSE TIME (s)
0.1
1.0
10
100
1000
Figure 13. Thermal Impedance for NDF04N62Z
LEADS
HEATSINK
0.110″ MIN
Figure 14. Isolation Test Diagram
Measurement made between leads and heatsink with all leads shorted together.
*For additional mounting information, please download the ON Semiconductor
Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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5
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