74LVC126APW,112 datasheet, PDF

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74LVC126APW,112: DescriptionBuffer/Line Driver 4-CH Non-Inverting 3-ST CMOS 14-Pin TSSOP Bulk; CategoryBuffer and line drives; File Size688KB，16 Pages; ManufacturerNexperia; Websitehttps://www.nexperia.com; Environmental Compliance

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74LVC126APW,112 Overview

Buffer/Line Driver 4-CH Non-Inverting 3-ST CMOS 14-Pin TSSOP Bulk

74LVC126APW,112 Parametric

Parameter Name	Attribute value
EU restricts the use of certain hazardous substances	Compliant
ECCN (US)	EAR99
Part Status	LTB
HTS	8542.39.00.01
Logic Family	LVC
Logic Function	Buffer/Line Driver
Number of Elements per Chip	4
Number of Channels per Chip	4
Number of Inputs per Chip	4
Number of Input Enables per Chip	0
Number of Outputs per Chip	4
Number of Output Enables per Chip	4 High
Bus Hold	No
Polarity	Non-Inverting
Maximum Propagation Delay Time @ Maximum CL (ns)	2.4(Typ)@3.3V\|2.7(Typ)@2.7V
Absolute Propagation Delay Time (ns)	15
Process Technology	CMOS
Input Signal Type	Single-Ended
Output Type	3-State
Maximum Low Level Output Current (mA)	24
Maximum High Level Output Current (mA)	-24
Minimum Operating Supply Voltage (V)	1.2
Typical Operating Supply Voltage (V)	2.5\|3.3\|1.8
Maximum Operating Supply Voltage (V)	3.6
Tolerant I/Os (V)	5
Typical Quiescent Current (uA)	0.1
Maximum Quiescent Current (uA)	40
Propagation Delay Test Condition (pF)	50
Maximum Power Dissipation (mW)	500
Minimum Operating Temperature (°C)	-40
Maximum Operating Temperature (°C)	125
Packaging	Bulk
Supplier Package	TSSOP
Pin Count	14
Mounting	Surface Mount
Package Height	0.95(Max)
Package Length	5.1(Max)
Package Width	4.5(Max)
PCB changed	14

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74LVC126A

Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

Rev. 8 — 8 April 2014

Product data sheet

1. General description

The 74LVC126A consists of four non-inverting buffers/line drivers with 3-state outputs,

which are controlled by the output enable input (nOE). A LOW at nOE causes the outputs

to assume a high-impedance OFF-state.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be

applied to the outputs.

2. Features and benefits



5 V tolerant inputs/outputs for interfacing with 5 V logic

Wide supply voltage range from 1.2 V to 3.6 V

CMOS low power consumption

Direct interface with TTL levels

Complies with JEDEC standard:



JESD8-7A (1.65 V to 1.95 V)



JESD8-5A (2.3 V to 2.7 V)



JESD8-C/JESD36 (2.7 V to 3.6 V)



ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115B exceeds 200 V



CDM JESD22-C101E exceeds 1000 V



Specified from

40 C

to +85

C

and

40 C

to +125

C

3. Ordering information

Table 1.

Ordering information

Package

Temperature range

74LVC126AD

74LVC126ADB

40 C

to +125

C

40 C

to +125

C

Name

SO14

SSOP14

TSSOP14

Description

plastic small outline package; 14 leads;

body width 3.9 mm

plastic shrink small outline package; 14 leads;

body width 5.3 mm

plastic thin small outline package; 14 leads;

body width 4.4 mm

Version

SOT108-1

SOT337-1

SOT402-1

SOT762-1

Type number

74LVC126APW

40 C

to +125

C

74LVC126ABQ

40 C

to +125

C

DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad flat package; no leads; 14 terminals;

body 2.5



0.85 mm

74LVC126APW,112 Related Products

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