MT54W512H36JF-3 datasheet, PDF

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MT54W512H36JF-3: DescriptionQDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165; Categorystorage storage; File Size414KB，28 Pages; ManufacturerCypress Semiconductor

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MT54W512H36JF-3 Overview

QDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165

MT54W512H36JF-3 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	BGA
package instruction	TBGA,
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	15 mm
memory density	18874368 bit
Memory IC Type	QDR SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX36
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	220
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	13 mm

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2 MEG x 8, 1 MEG x 18, 512K x 36

1.8V V

, HSTL, QDRIIb4 SRAM

18Mb QDR II SRAM

4-WORD BURST

Features

• DLL circuitry for accurate output data placement

• Separate independent read and write data ports with

concurrent transactions

• 100 percent bus utilization DDR READ and WRITE

operation

• Fast clock to valid data times

• Full data coherency, providing most current data

• Four-tick burst counter for reduced-address frequency

• Double data rate operation on read and write ports

• Two input clocks (K and K#) for precise DDR timing at

clock rising edges only

• Two output clocks (C and C#) for precise flight time

and clock skew matching—clock and data delivered

together to receiving device

• Optional-use echo clocks (CQ and CQ#) for flexible

receive data synchronization

• Single address bus

• Simple control logic for easy depth expansion

• Internally self-timed, registered writes

• Core V

= 1.8V (±0.1V); I/O V

Q = 1.5V to V

(±0.1V) HSTL

• Clock-stop capability with µs restart

• 13mm x 15mm, 1mm pitch, 11 x 15 grid FBGA package

• User-programmable impedance output

• JTAG boundary scan

™

MT54W2MH8J

MT54W1MH18J

MT54W512H36J

Figure 1: 165-Ball FBGA

Table 1:

Valid Part Numbers

DESCRIPTION

2 Meg x 8,QDRIIb4 FBGA

1 Meg x 18, QDRIIb4 FBGA

512K x 36, QDRIIb4 FBGA

PART NUMBER

MT54W2MH8JF-xx

MT54W1MH18JF-xx

MT54W512H36JF-xx

Options

• Clock Cycle Timing

3ns (333 MHz)

3.3ns (300 MHz)

4ns (250 MHz)

5ns (200 MHz)

6ns (167 MHz)

7.5ns (133 MHz)

• Configurations

2 Meg x 8

1 Meg x 18

512K x 36

• Package

165-ball, 13mm x 15mm FBGA

• Operating Temperature Range

Commercial (0°C

+70°C)

NOTE:

Marking

-3

-3.3

-4

-5

-6

-7.5

MT54W2MH8J

MT54W1MH18J

MT54W512H36J

None

1. A Part Marking Guide for the FBGA devices can be found on

Micron’s Web site—http://www.micron.com/numberguide.

The Micron

QDR™II (Quad Data Rate™) synchro-

nous, pipelined burst SRAM employs high-speed, low-

power CMOS designs using an advanced 6T CMOS

process.

The QDR architecture consists of two separate DDR

(double data rate) ports to access the memory array.

The read port has dedicated data outputs to support

READ operations. The write port has dedicated data

inputs to support WRITE operations. This architecture

eliminates the need for high-speed bus turnaround.

Access to each port is accomplished using a common

address bus. Addresses for reads and writes are latched

on alternate rising edges of the K clock. Each address

location is associated with four words that burst

sequentially into or out of the device. Since data can be

transferred into and out of the device on every rising

edge of both clocks (K and K# and C and C#) memory

bandwidth is maximized and system design is simpli-

fied by eliminating bus turnarounds.

General Description

18Mb: 1.8V V

, HSTL, QDRIIb4 SRAM

MT54W1MH18J_H.fm – Rev. H, Pub. 3/03

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