ADVANCE
2 MEG x 8
SMART 3 EVEN-SECTORED FLASH MEMORY
FLASH MEMORY
MT28F016S3
3V Only, Dual Supply (Smart 3)
FEATURES
• Thirty-two 64KB erase blocks
• Deep Power-Down Mode:
10µA MAX
• Smart 3 technology:
3.3V
±0.3V
V
CC
3.3V
±0.3V
V
PP
application programming
12V
±10%
V
PP
production programming
• Address access time: 120ns
• Industry-standard pinouts
• Inputs and outputs are fully TTL-compatible
• Automated write and erase algorithm
• Two-cycle WRITE/ERASE sequence
PIN ASSIGNMENT (Top View)
40-Pin TSOP Type I
OPTIONS
• Timing
120ns access
MARKING
-12
• Package
Plastic 40-pin TSOP Type 1 (10mm x 20mm) VG
Part Number Example:
A19
A18
A17
A16
A15
A14
A13
A12
CE#
V
CC
V
PP
RP#
A11
A10
A9
A8
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A20
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
V
CC
V
SS
V
SS
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
MT28F016S3VG-12
GENERAL DESCRIPTION
The MT28F016S3 is a nonvolatile, electrically block-
erasable (flash), programmable, read-only memory con-
taining 2,097,152 bytes (8 bits). Writing or erasing the
device is done with a 3.3V or 12V V
PP
voltage, while all
operations are performed with a 3.3V V
CC
. For back-
ward compatibility with SmartVoltage technology, 12V
V
PP
is supported for a maximum of 100 cycles and may
be connected for up to 100 cumulative hours. The
device is fabricated with Micron’s advanced CMOS
floating-gate process.
The MT28F016S3 is organized into 32 separately
erasable blocks. ERASEs may be interrupted to allow
2 Meg x 8 Smart 3 Even-Sectored Flash Memory
F51.p65 – Rev. 1/00
other operations with the ERASE SUSPEND command.
After the ERASE SUSPEND command is issued, READ
operations may be executed.
Operations are executed with commands from an
industry-standard command set. In addition to status
register polling, the MT28F016S3 provides a ready/
busy# (RY/BY#) output to indicate WRITE and ERASE
completion.
Please refer to Micron’s Web site (www.micron.com/
flash/htmls/datasheets.html) for the latest data sheet.
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
ADVANCE
2 MEG x 8
SMART 3 EVEN-SECTORED FLASH MEMORY
FUNCTIONAL BLOCK DIAGRAM
Input
8
Buffer
I/O
Control
Logic
64KB Memory Block (0)
64KB Memory Block (1)
64KB Memory Block (2)
Addr.
A0-A20
Buffer/
Latch
21
10
8
X - Decoder/Block Erase Control
11
Power
(Current)
Control
Addr.
Counter
Input
Data
Latch
DQ0-DQ7
CE#
OE#
WE#
RP#
V
CC
RY/BY#
V
PP
Command
Execution
Logic
State
Machine
Y-
Decoder
64KB Memory Block (29)
64KB Memory Block (30)
64KB Memory Block (31)
8
Y - Select Gates
8
Sense Amplifiers
Write/Erase-Bit
Compare and Verify
V
PP
Switch/
Pump
Status
Register
Identification
Register
Output
Buffer
2 Meg x 8 Smart 3 Even-Sectored Flash Memory
F51.p65 – Rev. 1/00
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
ADVANCE
2 MEG x 8
SMART 3 EVEN-SECTORED FLASH MEMORY
PIN DESCRIPTIONS
TSOP PIN
NUMBERS
38
SYMBOL
WE#
TYPE
Input
DESCRIPTION
Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW,
the cycle is either a WRITE to the command execution logic (CEL) or to the
memory array.
Chip Enable: Activates the device when LOW. When CE# is HIGH, the
device is disabled and goes into standby power mode.
Reset/Power-Down: When LOW, RP# clears the status register, sets the
internal state machine (ISM) to the array read mode and places the device
in deep power-down mode. All inputs, including CE#, are “Don’t Care,”
and all outputs are High-Z. RP# must be held at V
IH
during all other modes
of operation.
Output Enable: Enables data output buffers when LOW. When OE# is
HIGH, the output buffers are disabled.
Address Inputs: Select a unique, 8-bit byte out of the 2,097,152
available.
9
12
CE#
RP#
Input
Input
37
24, 23, 22, 21,
20, 19, 18, 17,
16, 15, 14, 13,
8, 7, 6, 5, 4, 3,
2, 1, 40
25-28,
32-35
36
OE#
A0-A20
Input
Input
DQ0-DQ7
RY/BY#
Input/
Output
Output
Data I/Os: Data output pins during any READ operation or data input
pins during a WRITE. Used to input commands to the CEL.
Ready/Busy: Indicates the status of the ISM. When RY/BY# = V
OL
, the ISM is
busy processing a command. If RY/BY# = V
OH
, the ISM is ready to accept a
new command. During deep power-down, device configuration read or
erase suspend, RY/BY# = V
OH
. Output is always active.
Write/Erase Supply Voltage: From a WRITE or ERASE CONFIRM until
completion of the operation, V
PP
must be at V
PPH
1
(3.3V) or V
PPH
2
(12V) (V
PP
≥
V
CC
). V
PP
= “Don’t Care” during all other operations.
Power Supply: +3.3V
±0.3V.
Ground.
No Connect: This pin may be driven or left unconnected.
11
V
PP
Supply
10, 31
29, 30
39
V
CC
V
SS
NC
Supply
Supply
–
2 Meg x 8 Smart 3 Even-Sectored Flash Memory
F51.p65 – Rev. 1/00
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
ADVANCE
2 MEG x 8
SMART 3 EVEN-SECTORED FLASH MEMORY
TRUTH TABLE
1
FUNCTION
Standby
Deep Power-Down/Reset
READ
READ
Output Disable
WRITE/ERASE
2, 3
ERASE SETUP
ERASE CONFIRM
4
WRITE SETUP
WRITE
5
READ ARRAY
6
DEVICE CONFIGURATION
Manufacturer Compatibility ID
Device ID
NOTE:
1.
2.
3.
4.
5.
6.
RP#
H
L
H
H
H
H
H
H
H
H
H
CE#
H
X
L
L
L
L
L
L
L
L
L
OE#
X
X
L
H
H
H
H
H
H
L
L
WE#
X
X
H
H
L
L
L
L
L
H
H
ADDRESS
X
X
X
X
X
BA
X
WA
X
000000H
000001H
V
PP
X
X
X
X
X
V
PPH
X
V
PPH
X
X
X
DQ0-DQ7
High-Z
High-Z
Data-Out
High-Z
20H
D0H
10H/40H
Data-In
FFH
89H
AAH
RY/BY#
V
OH
V
OH
V
OH
V
OH
V
OH
V
OH
→
V
OL
V
OH
V
OH
→
V
OL
V
OH
V
OH
V
OH
L = V
IL
(LOW), H = V
IH
(HIGH), X = V
IL
or V
IH
(“Don’t Care”).
V
PPH1
= 3.3V, V
PPH2
= 12V.
BA = Block Address; WA = Write Address.
Operation must be preceded by ERASE SETUP command.
Operation must be preceded by WRITE SETUP command.
The READ ARRAY command must be issued before reading the array after writing or erasing.
2 Meg x 8 Smart 3 Even-Sectored Flash Memory
F51.p65 – Rev. 1/00
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
ADVANCE
2 MEG x 8
SMART 3 EVEN-SECTORED FLASH MEMORY
FUNCTIONAL DESCRIPTION
The MT28F016S3 flash memory incorporates a num-
ber of features that make it ideally suited for system
firmware or data storage. The memory array is seg-
mented into individual erase blocks. Each block may be
erased without affecting data stored in other blocks.
These memory blocks are read, written and erased by
issuing commands to the command execution logic
(CEL). The CEL controls the operation of the internal
state machine (ISM), which completely controls all
WRITE, BLOCK ERASE and VERIFY operations. The ISM
protects each memory location from over-erasure and
optimizes each memory location for maximum data
retention. In addition, the ISM greatly simplifies the
control necessary for writing the device in-system or in
an external programmer.
The Functional Description provides detailed infor-
mation on the operation of the MT28F016S3 and is
organized into these sections:
•
•
•
•
•
•
•
•
•
•
•
•
Overview
Memory Architecture
Output (READ) Operations
Input Operations
Command Set
ISM Status Register
Device Configuration Registers
Command Execution
Error Handling
WRITE/ERASE Cycle Endurance
Power Usage
Power-Up
INTERNAL STATE MACHINE (ISM)
BLOCK ERASE and WRITE timing are simplified
with an ISM that controls all erase and write algorithms
in the memory array. The ISM ensures protection against
over-erasure and optimizes write margin to each cell.
During WRITE operations, the ISM automatically
increments and monitors WRITE attempts, verifies write
margin on each memory cell and updates the ISM status
register. When a BLOCK ERASE is performed, the ISM
automatically overwrites the entire addressed block
(eliminates overerasure), increments and monitors
ERASE attempts, and sets bits in the ISM status register.
ISM STATUS REGISTER
The ISM status register allows an external processor
to monitor the status of the ISM during WRITE and
ERASE operations. Two bits of the 8-bit status register
are set and cleared entirely by the ISM. These two bits
indicate whether the ISM is busy with an ERASE or
WRITE task and when an ERASE has been suspended.
Additional error information is set in three other bits:
V
PP
status, erase status and write status. These three bits
must be cleared by the host system.
READY/BUSY# (RY/BY#) OUTPUT
In addition to status register polling, the MT28F016S3
provides an asynchronous RY/BY# output to indicate
the status of the ISM. RY/BY# is V
OH
when the state
machine is inactive and V
OL
during a WRITE or ERASE
operation. This output is always active.
COMMAND EXECUTION LOGIC (CEL)
The CEL receives and interprets commands to the
device. These commands control the operation of the
ISM and the read path (i.e., memory array, device
configuration or status register). Commands may be
issued to the CEL while the ISM is active. However,
there are restrictions on what commands are allowed in
this condition. See the Command Execution section for
more detail.
DEEP POWER-DOWN MODE
To allow for maximum power conservation, the
MT28F016S3 features a very low current, deep power-
down mode. To enter this mode, the RP# pin is taken to
V
SS
±0.2V.
In this mode, the current draw is a maximum
of 10µA. Entering deep power-down also clears the
status register and sets the ISM to the read array mode.
OVERVIEW
SMART 3 TECHNOLOGY
Smart 3 technology allows maximum flexibility for
in-system READ, WRITE and ERASE operations. WRITE
and ERASE operations may be executed with a V
PP
voltage of 3.3V or 12V. Due to process technology
advances, 3.3V V
PP
is optimal for application and pro-
duction programming. For backward compatibility with
SmartVoltage technology, 12V V
PP
is supported for a
maximum of 100 cycles and may be connected for up
to 100 cumulative hours. For any operation, V
CC
is at
3.3V. However, no performance increase is realized.
THIRTY-TWO INDEPENDENTLY ERASABLE
MEMORY BLOCKS
The MT28F016S3 is organized into 32 indepen-
dently erasable memory blocks that allow portions of
the memory to be erased without affecting the rest of
the memory data.
2 Meg x 8 Smart 3 Even-Sectored Flash Memory
F51.p65 – Rev. 1/00
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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