MT9043AN datasheet, PDF - EEWORLD Datasheet

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MT9043AN: DescriptionTelecom Circuit, 1-Func, PDSO48, SSOP-48; CategoryWireless rf/communication Telecom circuit; File Size86KB，24 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

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MT9043AN Overview

Telecom Circuit, 1-Func, PDSO48, SSOP-48

MT9043AN Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Microsemi
Parts packaging code	SSOP
Contacts	48
Reach Compliance Code	unknown
JESD-30 code	R-PDSO-G48
Number of terminals	48
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Encapsulate equivalent code	SSOP48,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
power supply	3.3 V
Certification status	Not Qualified
Maximum slew rate	50 mA
Nominal supply voltage	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	DUAL

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MT9043

T1/E1 System Synchronizer

Preliminary Information

Features

•

Supports AT&T TR62411 and Bellcore GR-

1244-CORE, Stratum 4 Enhanced and Stratum

4 timing for DS1 interfaces

Supports ETSI ETS 300 011, TBR 4, TBR 12

and TBR 13 timing for E1 interfaces

Selectable 19.44 MHz, 1.544MHz, 2.048MHz or

8kHz input reference signals

Provides C1.5, C2, C4, C6, C8, C16, and C19

(STS-3/OC3 clock divided by 8) output clock

signals

Provides 5 different styles of 8 KHz framing

pulses

Attenuates wander from 1.9Hz

Fast lock mode

Provides Time Interval Error (TIE) correction

Accepts reference inputs from two independent

sources

JTAG Boundary Scan

DS5343

ISSUE 1

February 2000

Ordering Information

MT9043AN

48 Pin SSOP

-40 to +85

°C

•

Description

The MT9043 T1/E1 System Synchronizer contains a

digital phase-locked loop (DPLL), which provides

timing and synchronization signals for multitrunk T1

and E1 primary rate transmission links.

The MT9043 generates ST-BUS clock and framing

signals that are phase locked to either a 19.44 MHz,

2.048MHz, 1.544MHz, or 8kHz input reference.

The MT9043 is compliant with AT&T TR62411 and

Bellcore GR-1244-CORE, Stratum 4 Enhanced, and

Stratum 4; and ETSI ETS 300 011. It will meet the

jitter/wander tolerance, jitter transfer, intrinsic jitter,

frequency accuracy, capture range, phase change

slope,

and

MTIE

requirements

for

these

speciﬁcations.

•

Applications

•

Synchronization and timing control for

multitrunk T1,E1 and STS-3/OC3 systems

ST-BUS clock and frame pulse sources

OSCi

OSCo

TCLR

LOCK

VDD

VSS

Master Clock

TCK

TDI

TMS

TRST

TDO

PRI

SEC

IEEE

1149.1a

TIE

Corrector

Circuit

Virtual

Reference

DPLL

Output

Interface

Circuit

Reference

Select

MUX

Selected

Reference

TIE

Corrector

Enable

State

Select

Input

Impairment

Monitor

Reference

Select

RSEL

Control State Machine

State

Select

C19o

C1.5o

C2o

C4o

C6o

C8o

C16o

F0o

F8o

F16o

RSP

TSP

Feedback

Frequency

Select

MUX

RST

FLOCK

FS1

FS2

Figure 1 - Functional Block Diagram

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